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1/117 STA400A september 2003 front end interface n two internal 10 bit a/d converters n two qpsk demodulators for satellite branch n one multicarrier demodulator for terrestrial branch n satellite symbol frequency: 1.64 mbaud n terrestrial symbol frequency: 2.99 mbaud n digital root raised cosine nyquist filter: 15% roll-off n fft length: 768 sub-carriers n full digital carrier and frequency recovery and tracking loops n frequency inversion compensation for high-side/low-side mixer injection n lock detectors, c/n indicator, on chip ber estimators n two digital agcs: internal signal power estimation and filtering n 1 bit pdm agcs control signal outputs tdm decoding and management n satellite and terrestrial frame synchronization n satellite phase ambiguity resolution n tdm demultiplexing n prime rate channel (prc) demultiplexing n external memory controlling forward error correction n viterbi decoder: k=7, r=1/3 n satellite depuncturing: rate 3/4 n terrestrial depuncturing: rate 3/5 n convolutional time deinterleaver over 4.7 sec n block deinterleaver over 2 rs blocks n reed-solomon decoder: (255,223). up to 16 bytes correction capability. n energy dispersal descrambler n sat-sat and terr-sat diversity combining back end interface n two payload channel bitstream interfaces n payload channel selection logic n designed to work with the sta450a service and source decoder low power technology n 1.8v, 0.18 m m technology n 3.3v capable i/os control n iic-bus slave control interface n device address: 1101010 description the sdars is a satellite transmission system based on two geostationary satellites on the east and west coasts of the continental united states (conus). in the urban areas, where the line of sight reception of the satellites is difficult or not possible, the service is covered by terrestrial repeaters adopting a multicar- rier modulation scheme. designed for digital radio receivers compatible with the xmradio sdars system, the STA400A chan- nel decoder integrates all the functions to demodu- tqfp144 ordering number: STA400A this device can be sold only to customers that have signed a license agreement with xm satellite radio. xmradio ? sdars channel decoder
STA400A 2/117 late and decode the incoming satellite and terrestrial signals after the rf front-end down-convertions: analog- to-digital conversions, satellite and terrestrial demodulations, agcs, frame synchronization and demultiplexing, viterbi decoding, time and spatial diversity combining, reed-solomon decoding and deinterleaving, prime rate channel (prc) demultiplexing, payload channel (pc) selection. at the end of the demodulation and decoding processes a configurable serial data stream is made available to sta450a, the service/source decoder, via the pc bitstream interface. figure 1. channel decoder block diagram if2ta_p if2ta_n if2td[9:0] tagc if2sa_p if2sa_n if2sd[7:0] sagc adcsel terr.tdm synch. and descrambling sat2 tdm synch. and descrambling fifo fifo sat1&2 weighting factor calculation fifo mdq[7:0] madd[11:0] tdm decoding tdm management fec pcbs1 pcdc1 pcfs1 pcts_ef1 pcsd1 mreset xto xti/mclk intr scl sda mclko mclkon fifo pcbs2 pcdc2 pcfs2 pcts_ef2 pcsd2 sat1 tdm synch. and descrambling lock_s2 lock_s1 terr agc 10 bit adc 8 bit adc sat agc terrestrial multi carrier demodulator satellite 1 qpsk demodulator satellite 2 qpsk demodulator external memory controller tdm demux terr.fifo ber meas. sat.fifo sat/sat weighting & combining depuncturing viterbi decoder terr./sat. combining rs decoder microprocessor interface pc bitstream interface #2 pc bitstream interface #1 trefm trefp tadcref tincm tvcmo srefm srefp sadcref sincm svcmo mao1 mai1 mao2 mdqm mwe cas ras mcs1 mcs0 mcke mbs1 mbs0 prc demux controller mfp_clk clkd test_en sc an_ en bist_en ftesten ftestout[15:0] lock_m test interface clock distribution pc port #2 pc port #1
3/117 STA400A figure 2. pin connection (top view) pin description pin n pin name type function pad description [1:6] ftestout[10:15] o configurable functional test output 2ma output driver 7,40,55, 67,80,91, 115,129, vdd pwr 1.8v positive supply voltage 8,39,66, 81,102, 116,139 vdd3 pwr 3.3v positive supply voltage 9,31,41, 54,68,84, 90,101,107 ,114,128, 138 vss gnd digital ground ftestout10 ftestout11 ftestout12 ftestout13 ftestout14 ftestout15 vdd vdd3 vss trefm trefp tadcref tincm if2ta_p if2ta_n tvcmo avdd agnd svcmo if2sa_n if2sa_p sincm sadcref srefp srefm avdd agnd mreset tagc sagc vss xto xti/mclk adcsel mclko mclkon lock_s1 lock_s2 vdd3 vdd vss if2td9 if2td8 if2td7 if2td6 if2td5 if2td4 if2td3 if2td2 if2td1 if2td0 ftesten intr vss vdd clkd lock_m if2sd7 scl if2sd6 if2sd4 if2sd3 if2sd2 if2sd1 if2sd0 vdd3 if2sd5 vdd vss sda test_en scan_en bist_en pcts_ef2 pcfs2 pcsd2 pcdc2 pcbs2 pcts_ef1 vdd vdd3 pcfs1 pcsd1 vss pcdc1 pcbs1 mao1 mao2 nc vss vdd mai1 nc nc madd0 madd1 madd2 madd3 madd4 madd5 vss vdd3 madd6 madd7 madd8 madd9 vss mfp_clk 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 3 7 3 8 3 9 4 0 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 4 9 5 0 5 1 5 2 5 3 5 4 5 5 5 6 5 7 5 8 5 9 6 0 6 1 6 2 6 3 6 4 6 5 6 6 6 7 6 8 6 9 7 0 7 1 7 2 1 3 2 1 3 6 1 0 9 1 1 0 1 1 1 1 1 2 1 1 3 1 1 4 1 1 5 1 1 6 1 1 7 1 1 8 1 1 9 1 2 0 1 2 1 1 2 2 1 2 3 1 2 4 1 2 5 1 2 6 1 2 7 1 2 8 1 2 9 1 3 0 1 3 1 1 3 3 1 3 4 1 3 5 1 3 7 1 3 8 1 3 9 1 4 0 1 4 1 1 4 2 1 4 3 1 4 4 madd10 madd11 mbs0 mbs1 mcke vss vdd vdd3 mcs0 mcs1 mdqm mdq0 mdq1 mdq2 mdq3 mdq4 mdq5 mdq6 mdq7 vss vdd ras cas mwe ftestout0 ftestout1 ftestout2 ftestout3 ftestout4 vss vdd3 ftestout7 ftestout8 ftestout9 ftestout6 ftestout5
STA400A 4/117 10 trefm analog vref terr. adc reference negative voltage. bottom of the reference ladder (driven or filtered). analog pad buffer (1) 11 trefp analog vref terr. adc reference positive voltage. top of the reference ladder (driven or filtered). analog pad buffer (1) 12 tadcref analog terminal terr. adc reference adjust (external resistor to determine ipol) analog pad buffer (1) 13 tincm analog output terr. adc internal common-mode output for bypassing analog pad buffer (1) 14 if2ta_p analog input terr. 2nd if differential input - positive analog pad buffer (1) 15 if2ta_n analog input terr. 2nd if differential input - negative analog pad buffer (1) 16 tvcmo analog terminal terr. adc internal common mode (filtered) analog pad buffer (1) 17,26 avdd pwr analog positive supply voltage (1.8v) 18,27 agnd gnd analog ground 19 svcmo analog terminal sat. adc internal common mode (filtered) analog pad buffer (1) 20 if2sa_n analog input sat. 2nd if differential input - negative analog pad buffer (1) 21 if2sa_p analog input sat. 2nd if differential input - positive analog pad buffer (1) 22 sincm analog output sat. adc internal common-mode output for bypassing analog pad buffer (1) 23 sadcref analog terminal sat. adc reference adjust (external resistor to determine ipol) analog pad buffer (1) 24 srefp analog vref sat. adc reference positive voltage. top of the reference ladder (driven or filtered). analog pad buffer (1) 25 srefm analog vref sat. adc reference negative voltage. bottom of the reference ladder (driven or filtered). analog pad buffer (1) 28 mreset i master reset schmitt trigger buffer 29 tagc o terr. agc control signal 2ma output driver 30 sagc o sat. agc control signal 2ma output driver 32 xto o xtal output oscillator buffer 33 xti/mclk i xtal input or master clock input analog pad buffer (2) 34 adcsel i selection between internal or external adc 0=internal buffer with pull-down pin n pin name type function pad description pin description (continued)
5/117 STA400A 35 mclko o master clock output 4ma output driver 36 mclkon o inverted master clock output 4ma output driver 37 lock_s1 o satellite dem1 lock indicator 2ma output driver 38 lock_s2 o satellite dem2 lock indicator 2ma output driver [42:51] if2td[9:0] i terr. 2nd if digital input input pad buffer. high drive. 52 ftesten i functional test enable (1=enable) buffer with pull-down 53 intr o interrupt 2ma output driver 56 clkd o divided master clock 2ma output driver 57 lock_m o terrestrial demodulator lock indicator 2ma output driver [58:65] if2sd[7:0] i sat. 2nd if digital input input pad buffer. high drive 69 scl i iic-bus serial clock schmitt trigger buffer 70 sda i/o iic-bus serial data schmitt trigger bidir buffer. 4ma driver 71 test_en i atpg test enable (1=enabled) buffer with pull-down 72 scan_en i scan enable (1=enabled) buffer with pull-down 73 bist_en i ram bilt in self test enable (1=enabled) buffer with pull-down 74 pcts_ef2 o payload channel tscc sync2/errorflag 2 (432 msec) 2ma output driver 75 pcfs2 o payload channel prc frame sync 2 2ma output driver 76 pcsd2 o payload channel serial data 2 2ma output driver 77 pcdc2 o payload channel data clock 2 2ma output driver 78 pcbs2 o payload channel byte sync2 (rs symbol) 2ma output driver 79 pcts_ef1 o payload channel tscc sync1/ errorflag1 (432 msec) 2ma output driver 82 pcfs1 o payload channel prc frame sync1 2ma output driver 83 pcsd1 o payload channel serial data 1 2ma output driver 85 pcdc1 o payload channel data clock 1 2ma output driver 86 pcbs1 o payload channel byte sync1 (rs symbol) 2ma output driver 87 mao1 o mobile adapter output #1 2ma output driver 88 mao2 o mobile adapter output #2 2ma output driver 89,93,94 nc not connected. 92 mai1 i mobile adapter input buffer with pull-down pin n pin name type function pad description pin description (continued)
STA400A 6/117 1. direct connection to core 2. connected to the internal oscillator buffer via 460 ohm series resistor absolute maximum ratings thermal data notes: 1. according to jedec specification on a 4 layers board [95:100] madd[0:5] o external memory address 2ma output driver [103:106] madd[6:9] o external memory address 2ma output driver 108 mfp_clk o tdm master frame clock 2ma output driver [109:110] madd[10:11] o external memory address 2ma output driver [111:112] mbs[0:1] o external memory block selection 2ma output driver 113 mcke o external memory clock enable 2ma output driver [117:118] mcs[0:1] o external memory chip select 2ma output driver 119 mdqm o external memory data mask 2ma output driver [120:127] mdq[0:7] i/o external memory data input output bidir buffer. 2ma driver 130 ras o external memory row address strobe 2ma output driver 131 cas o external memory column address strobe 2ma output driver 132 mwe o external memory write enable 2ma output driver [133:137] ftestout[0:4] o configurable functional test output 2ma output driver [140:144] ftestout[5:9] o configurable functional test output 2ma output driver symbol parameter value unit v dd, av dd 1.8v power supply voltage -0.5 to 2.5 v v dd3 3.3v power supply voltage -0.5 to 4 v v i voltage on input pin -0.5 to (vdd3 + 0.5) v v o voltage on output pin -0.5 to (vdd3 + 0.5) v v ia voltage on analog input pin -0.8 to (avdd + 0.8) v v oa voltage on analog output pin -0.8 to (avdd + 0.8) v t stg storage temperature -55 to +150 c t oper operative ambient temperature -40 to +85 c t j operative junction temperature -40 to +125 c symbol parameter value unit r j-amb thermal resistence junction to ambient (1) 40 oc/w pin n pin name type function pad description pin description (continued)
7/117 STA400A dc electrical characteristcs: (t amb = -40 to +85c, v dd = av dd = 1.65 to 1.95v, v dd3 = 3.0 to 3.6v unless otherwise specified). note 1: performed on all the input pins excluded the pull-down ones note 2: performed on the i/o pins in tristate mode note 3: guaranteed by design note 4: take into account 200mv voltage drop in supply lines and input/output levels for frequency > 20mhz. note 5. x is the source/sink current under worst case conditions (x = 2 to 4 ma) note 6: human body model note 7. guaranteed by ipd measurements symbol parameter conditions min typ max unit v dd 1.8v supply voltage 1.65 1.8 1.95 v v dd3 3.3v supply voltage 3.0 3.3 3.6 v av dd 1.8v analog supply voltage 1.65 1.8 1.95 v i dd v dd power supply current mclk = 23.92mhz; sat1, sat2 & terr arms active; v dd =1.95v 130 160 ma i dd3 v dd3 power supply current mclk = 23.92mhz; sat1, sat2 & terr arms active; v dd3 =3.6v 45 90 ma i avddsat av ddsat power supply current mclk = 23.92mhz; v in =0.75vpp; f in =6.095mhz; av ddsat =1.95v 16 20 ma i avddterr av ddterr power supply current mclk = 23.92mhz; v in =0.75vpp; f in =2.99mhz; av ddterr =1.95v 16 20 ma p d power dissipation mclk = 23.92mhz; v dd = 1.8v; v dd3 = 3.3v 350 mw i il low level input leakage current 1) vi = 0v 1 m a i ih high level input leakage current 1) vi = v dd3 1 m a i oz tristare output leakage current 2) vo = 0v or v dd3 1 m a i pd pull-down current vi = v dd3 30 110 m a r pu equivalent pull-up resistance 7) vi = 0v 50 k w r pd equivalent pull-down resistance 7) vi = v dd3 50 k w v il low level input voltage 0.8 v v ih high level input voltage 2 v v ilhyst low level threshold input falling 0.8 1.35 v v ihhyst high level threshold input rising 1.3 2 v v hyst schmitt trigger hysteresis 3) 0.3 0.8 v v ol low level output voltage 4,5) iol = xma 0.2 v v oh high level output voltage 4,5) ioh = xma 2.8 v c in input capacitance 3) 1.2 pf c out output capacitance 3) 1.9 pf c io i/o (bi-directional) capacitance 3) 2.1 pf i latchup i/o latch-up current 200 ma v esd electrostatic protection 6) leakage<1 m a 4000 v
STA400A 8/117 adc electrical characteristcs: (t amb = -40 to +85c, v dd =1.8v, av dd = 1.65 to 1.95v, v dd3 = 3.3v unless otherwise specified adc analog input adc reference voltage adc accuracy adc dynamic characteristics note1: input resistance from conversion frequency f c : r in = (35k w x 75mhz)/f c note2: guaranteed by design master clock input electrical characteristcs: (t amb = -40 to +85c, v dd =1.65 to 1.95v, av dd = 1.65 to 1.95v, v dd3 = 3.0 to 3.6v unless otherwise specified) symbol parameter conditions min typ max unit if2xa_p, if2xa_n voltage range 0.75 vpp xincm internal common mode 0.375 0.625 v r in (1) input resistance 2) @75mhz 35 k w c in input capacitance 2) 800 ff bw analog bandwidth 2) 200 mhz symbol parameter conditions min typ max unit xrefp top internal voltage reference 0.75 50mv v xrefm bottom internal voltage reference 0v symbol parameter conditions min typ max unit dnl differential non-linearity tamb = 25c ; av dd = 1.8v -1.5 0.9 1.5 lsb inl integral non-linearity tamb = 25c; av dd = 1.8v -2.0 1.5 2.0 lsb symbol parameter conditions min typ max unit snr signal to noise ratio 2) fs = 75msps, fin = 15mhz; av dd = 1.8v 57 db sinad signal to noise and 2) distortion ratio fs = 75msps, fin = 15mhz av dd = 1.8v 56 db thd total harmonic distortion 2) fs = 75msps, fin = 15mhz av dd = 1.8v 57 db enob effective number of bit 2) fs = 10msps, fin = 10mhz av dd = 1.8v 9.5 bit symbol parameter conditions min typ max unit v mclk master clock input voltage swing 0.8 1 1.2 vpp v mclkofs master clock input voltage offset vdd/2 v
9/117 STA400A oscillator buffer electrical characteristics the oscillator pad buffer is a single stage oscillator with an inverter working as an amplifier biased by an internal resistor (>1 mohm). with an external pi network consisting of a crystal and two capacitors it works as oscillator, without the external crystal component it acts as input trigger. pin xti (analog pad buffer) is the input for the external clock source or for the quartz component, xto is the oscillator buffer output pin to be connected to the external quartz. oscillator mode specification (guaranteed by design) condition: 27 mhz oscillation - pi quartz network connected to xti and xto (c a = c b = 16pf). input trigger mode specification (no crystal connected) (guaranteed by design) condition: 27 mhz sine wave (0.5v amplitude, vdd/2 offset) applied to xti. the external analog signal to be applied to the xti input must be a sinusoid or a impulse wave centered at vdd/ with 1v peak-to-peak amplitude. minimum oscillator transconductance (guaranteed by design) the oscillator pad buffer can work with different crystal frequencies. to check if a given quartz can be used with this oscillator, the needed amplifier transconductance must be evaluated by the following formula: if the equation simplifies to: where r m is the quartz equivalent series resistance, c a and c b the pi network capacitances and c o the quartz shunt capacitance. the transconductance of the oscillator pad given in the table above must be 8/9 times the transconductance calculated with the formula. symbol parameter min typ max unit ci current consumption 450 m a cp power consumption 810 m w dc duty cycle 49.07 49.60 49.86 % t start-up start-up time 3 ms symbol parameters vl vh hysteresis unit hys hysteresis 0.631 1.123 0.492 v symbol parameters min typ max unit ci current consumption 133 m a cp power consumption 240 m w dc duty cycle 49.45 % symbol patrameters min typ max unit gmcrit 1236 m a/v gm crit r m w 2 c a c b c a c o c b c o + + () 2 c a c b -------------------------------------------------------------------------------- - = c a c b c == gm crit r m w 2 c2c o + () 2 =
STA400A 10/117 1 functional description the main inputs of the STA400A channel decoder are the 2nd if analog signals centered at 6.095 mhz for the satellite and at 2.99 mhz for the terrestrial branch. the final down-convertion to baseband of the three signals is digitally performed inside the chip. after the demodulation process, the three tdm data streams are available and stored into the external memory for further digital processing including tdm decoding and demultiplexing, time and spatial diversity combining, fec processing and data stream generation for the external source de- coding. the external memory and the prc-based packed structure of the service layer allow the use of one viterbi decoder and rs decoder for the fec processing of both the combined satellite and terrestrial frames. the STA400A is designed to work with the sta450a service/source decoder, an external rf tuner and a 128mbit synchronous dram. figure 3 depicts the connection block diagram of the STA400A channel decoder and the external components. the 128mbit sdram may be selected as a single 4mx8bitx4banks or as a dual 2mx8bitx4banks memory. in the latter case the mcs0 pin must be connected to the chip select input of the memory and the xmem_type register (address 0x0630) must be programmed with "0x01" (see section 2.8). STA400A is fully configurable via the i2c-bus interface. figure 3. STA400A connection diagram the 23.92 mhz system clock applied to xti/mclk input (pin 33) can be generated by the built-in clock buffer and an xtal pi-network as showed in fig.3 or may come from an external source. in both cases the quartz or the external source must be compliant with the specifications given in the i/o cell description (section 3). in fig.3 the two embedded 10 bits adcs are used to sample and convert to digital the satellite and terrestrial if signals from the tuner. an internal mux, controlled by the adcsel input (pin 34), may be used to by-pass the tuner 10k 10k 1u 1u terr adc diff. input sat adc diff. input agcs control sta400 sta450 if2ta_n if2sa_p if2sa_n tagc sagc adcsel pcsd1 pcsd pcdc1 pcdc mfp_clk pll_sync mclko clk_in data line clk line sdram#0 if2ta_p madd[11:0] address bus - 12 data bus - 8 mdq[7:0] bank address - 2 mbs[1:0] i/o mask - 1 mdqm mwe cas ras command inputs - 3 mcs0 mcs1 chip select chip select mclkon mcke clock clock enable mao1 mao2 sdram#1 mai1 scl sda intr to microcontroller iic clock line iic data line interrupt line if2sd[7:0] if2td[9:0] if2ta_p ftestout[15:0] to functional test interface xti/mclk xto mobile adapter 22pf 22pf 23.92 mhz from external source adcsel pcfs1 pcfs pcts_ef1 pcts_ef
11/117 STA400A two embedded adcs. this functionality gives the possibility to use two external adcs connected to the satellite digital input (if2sd[7:0]) and to the terrestrial digital input (if2td[9:0]) respectively. the digital inputs must be tied to ground when not used. the ftestout[15:0] pins are available for testing purpose and for measuring system performance. 1.1 if sampling and control interface this block comprises the embedded adcs, the satellite and terrestrial agcs and cdec control registers. it receives from the rf front-end the two qpsk modulated satellite signals centered at 6.095 mhz and the mul- ticarrier modulated terrestrial signal centered at 2.99 mhz (2nd if frequencies). these signals are over sampled by the 23.92 mhz master clock (mclk) and converted to digital on 8 bits for the satellite composite signal and on 10 bits for the terrestrial signal (see fig.1). the programmable registers of the if sampling block are described in section 2.6. embedded adcs the two embedded adcs are 10 bit high speed a/d converters designed for high sampling rate (up to 50 mhz) and low power consumption (1mw/mhz) with a full differential pipeline conversion architecture that needs 6 clock periods for one conversion. a voltage reference is integrated in the circuit for external components minimization but it is possible to use an external reference. the adcs provide also a reduced input capacitance, a low reference capability and a wide input bandwidth (50mhz). pins if2xa_p if2xa_n can be connected as full-differential inputs or as pseudo-differential input. in fig.4 the latter configuration is showed (x=s for satellite and x=t for terrestrial branch). figure 4. adc pseudo-differental configuration the two pins xrefm (bottom of the reference ladder) and xrefp (top of the reference ladder) are decoupling nodes for conversion dynamic adjustment; when the internal reference is used these pins must be connected as showed in figure 4. pin xadcref is connected with an external resistor (typical value 47 kohm) to trim the internal bias current, xincm is the output common mode used to centre the external input network and xvcmo is the internal common mode that can be externally filtered by a capacitor. 27pf 47pf 33ohm 50ohm vin 100nf 2.2uf 47k 33ohm 50ohm xvcmo xrefp data[9:0] xrefm if2xa_n if2xa_p xincm xadcref 100pf 100nf 100nf 100pf from internal clk distribution
STA400A 12/117 if agc to maintain constant the signal levels at the a/d converters input, two 1-bit pulse density modulated (pdm) signals (sagc for satellite and tagc for terrestrial branch) are generated to drive an external if agc. the difference between the user programmable reference level and the power of the input samples is integrated by the programmable gain loop filter and then sent to a 1-bit modulator to generate the output control signal. the sense of this signal is programmable to adapt it to a positive or negative slope of the variable gain amplifier. the sagc and tagc outputs can be filtered by an external low pass filter to close the agc loop (see fig.3); in this way the mean power of the adcs input signal is forced to the reference. the agc loop gain is given by: b agc = 2 xagcbeta . the parameter xagcbeta can take values from 0 to 6. when xagcbeta="111" the loop gain is zero. the agc loop may be opened by programming "111" in the x agcbeta parameter and writing "00000000" in the xagcintg register. in this condition the control signal is a 50% duty-cycle square wave with a frequency of mclk/2 (23.92mhz/2=11.96mhz). the 8 msbs of the integrator register may be read at any time in the xagcintg register. this value is the level of the agc outputs after low pass filtering; it gives an image of the input signal power at the terrestrial and sat- ellite branch respectively. the reference level can be set by the xagcref register, the loop gain and the sense of the control pins (tagc and sagc) are set by the agc_ctrl1 register described in section 2.6. control registers the if_ctrl, control and status1 are the control registers of the if sampling interface (see section 2.6). to have a more stable reading of the xagcintg register a moving average filter over 2048 samples is used. this filter can be enabled or disabled by the bit7 of the if_ctrl register. the data bit from the external adcs (if used) may have a two's complement or offset binary format. bit1 of the if_ctrl register sets the binary format for the digital if inputs. the control register configures the master clock outputs (mclko and mclkon) and the external memory mode access of the bi-directional bus (mdq[7:0]). when the master clock output buffers are disabled the output levels are fixed to ground resulting in no activity on these pins; this aproach minimizes the interferences when these signals are not used. the bi-directional buffers of the STA400A and the input/output mask of the external sdram are controlled by the mdqm pin. the STA400A has a low level active bi-directional buffers (high level on the enable drives the buffers to hi-z). the input/output mask operation of the external sdram may be selected active high or active low (see figure 5) setting the mdqm_ctrl parameter of the control register (bit5). figure 5. input/output mask configuration mdqm_ctrl data output register 1 0 mdq[7:0] mdqm sta400 sdram mdq bidir buffer mdqm output buffer data input register i/o mask STA400A
13/117 STA400A the carrier lock indication of the satellite and the terrestrial demodulators, and the status of the fec terrestrial- satellite combining may be read in the status1 register described in section 2.6. 1.2 satellite demodulation the satellite signals are demodulated by two qpsk demodulators, one tuned to the east satellite and the other to the west satellite. the two qpsk demodulators are identical and include quadrature demodulation, carrier and timing recovery and tracking, frequency sweep generation, nyquist root raised cosine filtering with 15% roll-off, digital agc, lock indication and carrier to noise estimation. figure 6. satellite demodulator block diagram the architecture of one qpsk demodulator is depicted in fig.6. the input signal, sampled at 23.92 mhz and quantized on 8 bits, is multiplied by the sine an cosine functions to obtain the in-phase and the quadrature com- ponent of the transmitted symbols. the demodulated qpsk signal is affected by the phase and frequency error due to oscillator inaccuracies and frequency shift. these errors are removed by the carrier tracking loop by means of a phase/frequency detector, a loop filter and an nco. the symbol tracking loop removes the phase and frequency uncertainties in the symbols: instead of controlling the sampling clock phase, the timing error de- tector adjusts, using the timing nco, the impulse response phase of the two interpolator filters. to enhance the performace of the demodulator in presence of a signal dropout, the carrier and symbol loops are controlled by the carriernulloffset and the timingctrl blocks. the first operates on the carrier nco and carrier loop filter, the latter on the timing loop filter. an internal ramp generator (freqsweep) is used to help the carrier loop during the acquisition phase. the fre- quency sweep is stopped by the lock detector output whenever a lock condition is reached. the phase ambiguity introduced by the demodulation process and the frame synchronization are resolved in the tdm decoding block using the master frame preamble (mfp) and the fast syncronization preamble (fsp). symbol clock lock_sx pin 37/38 new iffreq iout qout rrc interpolator filter rrc interpolator filter c/n estim up agc2ref + - agc2beta limiter reg agc2intg to tdm decoding agc2 loop i +q 22 symfreq reg timing nco up up up up up up timintg ctrl freq sweep carrier null offset disable up clear lock detect phase error detector timing error detector up sin/cos rom qchs i/q mixer - carrier nco reg iffreq reg reg carfreq up reg from if sampling up + + limiter reg beta_m up l-shift up carintg up alphacar reg up beta_e carrier loop filter betacar + + limiter reg beta_m up l-shift up timintg up al fatim reg up beta_e timing loop filter betatim
STA400A 14/117 the second if composite satellite signal, available at the if2sa inputs, has the spectrum schematically shown in fig.7. the base band convertion of the selected satellite signal is done by programming the carrier nco (act- ing as local oscillator) of the demodulator. for demodulating the s1-early satellite signal the carrier nco fre- quency of the early qpsk demodulator must be equal to 6.095 + 0.92 = 7.015 mhz; for the s2-late satellite signal the frequency at the carrier nco output of the late qpsk demodulator must be 6.095 - 0.92 = 5.175 mhz. the register map of the qpsk demodulators is described in section 2.2. i/q mixer - carrier nco the final downconvertion to baseband of the 2nd if satellite signal is performed by a mixer and a local oscillator implemented with an nco and a sin/cos look-up table (see figure 6). the signal coming from the if sampling block is multiplied by the output of the quadrature nco to produce the i and q components of the baseband signal. the nco output are the sine and cosine functions obtained with a look-up table driven by a 28 bit phase accumulator. the iffreq register sets the frequency of the carrier nco as given in the following: f c = f mclk x (iffreq)/2 28 , where f mclk is the clock frequency and iffreq is the 28 bit integer value loaded in the register. for example, to program the s1-nco to 7.015 mhz the iffreq register must be loaded with 04b13b14 (hex) equivalent to 78723860 (dec). the sine/cosine output frequency of the nco is given by f o = (f c + f sw + ph err ) x f mclk /2 28 where fc is the nominal center frequency, f sw is the output of the frequency sweep generator, pherr is the filtered phase error from the carrier loop filter output and f mclk /2 28 is the nco frequency resolution. the carfreq read only register gives the value of the actual carrier frequency after the lock condition has been reached. this register can be used to measure the frequency offset between the local oscillator and the incoming carrier. the qchs block of the i/q mixer changes the sign of the quadrature component in order to adapt the demod- ulation process to a different rotation sense of the qpsk mapping. figure 7. second if satellite signal spectrum fo s1a (s1b) f (mhz) s2a (s2b) fo + 0.92 fo - 0.92 fo = 6.095 mhz rrc symbol freq = 1.64 mhz roll-off factor = 15 % s2 = late satellite s1 = early satellite a = ensemble a; b = ensemble b 3.726 1.886 1.886 1.64 1.64 1.84 0.92 0.92
15/117 STA400A high-side/low-side injenction control in a superetherodyne tuner (using two downconversions to produce the second if signal at the channel decod- er satellite input) is possible that one lo may use an high-side injection of the carrier and the other lo may use a low-side injection. in this case a data polarity convertion is required in the channed decoder. to accomodate this function two methods are available: the first method requires a polarity change in the qchs and carchs bits of the qpsk_ctrl register, with the second method the iffreq register of the carrier nco must be programmed with the image frequency using the following formula: f mclk - f c = f mclk x (iffreq)/2 28 for example, to set the image frequency of the 7.015 mhz the value fb4ec4ec (hex) must be loaded in the iffreq register. matched/interpolator filters the STA400A provides two matched/interpolator filters. these filters perform the nyquist filter function (matched with the one in the transmission side) with a root raised cosine (rrc) shape and a roll-off factor of 15% and the interpolation function to evaluate the optimum sampling instant of the output symbol. the filters, based on a poliphase structure (12 taps with 32 coefficients/ tap), receive at their inputs the separate i and q streams at f mclk /f sym samples/symbols and produce the separate i and q output streams at one sample per symbol. the frequency responce of one filter is given in fig.8 and fig.9. agc2 the agc2 loop is designed to maintain a fixed signal level at the input of the soft decision slicer. as shown in fig.6, the agc2 loop consists of an error detector, a loop filter and a gain multiplier. the modulus of the complex symbols is compared to a programmable reference level (agc2ref register) and then scaled by the agc2beta coefficient and integrated. the filtered error drives two multipliers at the output of the matched filters to maintain constant the level at the demodulator output. the agc2 loop gain is given by: b agc2 = 2 agc2beta . the parameter agc2beta can take values from 0 to 6. when agc2beta="111" the loop gain is null and the agc2 amplifier gain keeps the last value. the agc loop may be opened by programming "111" in the agc2beta parameter and writing "0x00" in the agc2intg reg- ister. the reference level set in the agc2ref register impacts on the carrier and timing loop equations and on the operation of the soft decision slicer. figure 8. rrc filter frequency responce 0 200 400 600 800 1000 1200 1400 1600 1800 2000 60 50 40 30 20 10 0 frequency (khz) magnitude (db) 3 815 khz
STA400A 16/117 figure 9. rrc filter passband ripple carrier phase/frequency error detector the carrier phase/frequency error detector (pfd) measures the error between the sampled symbols and the quadrant bisector. the error is calculated by the following formula : ph err = i x sgn(q) - q x sgn(i), where sgn(.) is the sign function. this value is computed at symbol rate if the actual i and q components are greater than a programmed thresh- old otherwise the previous value is maintained. in this way the detector outputs a dc value proportional to the frequency offset between the incoming signal and the local oscillator. in the steady state, when the carrier loop is locked (and, therefore, the phase error is small), the circuit behaves like a pure phase detector while during the acquisition phase it behaves like a pfd. the threshold value may be programmed by the pfdthr register. the signal level after the agc2 loop must be taken into account when setting the threshold. the default preset for this parameter is about the 20% of the agc2 reference value (see agc2ref register). the carrier phase and frequency detector gain (k d ) characteristic as a function of the carrier to noise ratio is given in fig.10. k d = 1.24 is the value for a noise free input signal and may be reduce up to 50% of its maximum value in a low c/n condition. figure 10. carrier phase/frequency detector gain 0 100 200 300 400 500 600 700 800 900 1000 1 0.5 0 0.5 frequency (khz) magnitude (db) 0 2 4 6 8 10 12 14 16 18 20 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 c/n (db) pfd gain
17/117 STA400A carrier loop filter the carrier loop filter is a first order iir filter with two programmable parameters, one for the proportional and the other for the integral correction, as shown in fig. 6. the output of the integrator, that produces a frequency control term, is summed with the weighted phase error in the proportional path and then sent to the carrier nco to close the carrier tracking loop. the proportional gain alpha and the integral gain beta of the filter are configured by the registers alfacar and betacar respectively. the integral gain is set by a mantissa and exponent as given by: beta = beta_m x 2 (beta_e) where beta_m, the mantissa, is a 5-bit integer value set in the five lsbs of the betacar register (beta_m=be- tacar[4:0]) and beta_e, the exponent, is a 3-bit integer set in the three msbs of the betacar register (beta_e=betacar[7:5]). the proportional gain is an integer value set in the alfacar register with a range from 0 to 255 (alpha=alfa- car[7:0]). the carintg register collects the 8 msbs of the filter integrator and may be read or written at any time by the system controller. when the register is written, the integrator lsbs are reset. the filter integrator is saturated to 21-bit by the limiter block resulting in a maximum peak-to-peak frequency range of 373khz (with f mclk = 23.92mhz). carrier loop equations the carrier loop is fully digital and comprises two blocks working at symbol rate: the phase/frequency error detector and the loop filter, and two blocks working at clock rate: the carrier nco and the i/q mixer (see fig.6). the loop is parametrised by the coefficients alpha and beta given in the registers alfacar and betacar respectively. the carrier loop is a second order loop whose natural frequency f n and damping factor x may be calculated applying the following formulas: where alpha is set in the alfacar register and beta in the betacar register, k d is the pfd gain as shown in fig.10 and m is the reference level of the agc2 loop (see agc2ref register). for example, to set the loop natural frequency to 1.3khz with the default value for m=agc2ref (90dec, 5ahex) and k d = 1.24 (noise free value), the above equation solved for beta gives: alpha can be chosen to have a damping factor equal to 0.7: the register alfacar can be programmed with 23 (dec) and the register betacar can be programmed with the parameter beta_e=0 and beta_m=21 (dec). frequency sweep when the frequency offset is greater than the pull-in range of the carrier loop or in presence of low signal to noise ratio the tracking performance of the loop itself may became rather slow. to help the loop in tracking this frequency offset an internal frequency sweep generator can be enabled via iic-bus. the output of this block is summed to the frequency register of the i/q mixer and operates only during the carrier acquisition. the sweep is stopped by the lock detector when the carrier lock condition is reached (see fig.6). the sweep rate is given by the following formula: f n 26.96 mk d beta [hz ] = z 0.01322 alpha mk d beta ------------ - = beta f n 2 726.84mk d ------------------------------ - 20.83 == alpha z 0.01322 --------------------- beta mk d ------------ - 22.87 ==
STA400A 18/117 the frequency sweep operation is controlled by the rampctrl register. the parameter swstep can take 0 or 1 values and stepper can be programmed in the range 0 to 15 decimal. the maximum peak-to-peak frequency sweep range is 373.75khz. the sweep direction can be positive or neg- ative depending on the bit-6 of the rampctrl register. the sweep always starts from the zero value; when the upper limit is reached, the sweep continues with the lower one if the positive slope is set and viceversa when the negative slope is selected. this frequency sweep block can be switched on or off setting the swon parameter to 1 or 0 respectively. when swon=0 the output value of the ramp is null. carrier lock detector the lock detector consists of an up/down counter with saturation driven by a dedicated logic. this circuit moni- tors the qpsk symbol constellation to decid the counter direction. if the actual symbol is inside the region de- limited by the equations 2 x i - q 3 0 and 2 x q - i 3 0 (the lock region) the counter counts up otherwise counts down. if the demodulator is locked, the number of symbols inside the lock region is greater than the number of symbols outside and the the counter is driven in the up direction toward the saturation limit. when the counter output is above a programmable threshold, the lock indicator is set to '0' declaring the lock condition of the car- rier tracking loop. this threshold is set by the lockthr register. the lock detector controls the frequency sweep generator, the carrier null offset and timing_ctrl circuits. timing nco the timing nco is the timing generator for the two interpolator filters (see fig.6). to correct the symbol error, the impulse response of the interpolator is shifted by an amount of time depending on the phase accumulated in the timing nco. it consists of a 25-bit modulo-1 accumulator driven by the output of the timing loop filter. the 5lsbs of the accumulator give the fractional part of the sampling clock used by the interpolator filter to select the coefficients of the impulse response that cancel the timing error. the integer part, given by the carry bit of the accumulator, is used to decimate to symbol rate the output of the interpolator/matched filter. the nominal symbol frequency is set by the symfreq register. the timing loop adjusts this nominal value to find the optimal symbol phase (maximum open eye condition) and to track the residual symbol frequency offset. the output of the timing generator is given by f o = (f sym + ted err ) x f mclk /2 25 where f sym = 1.64mhz is the nominal symbol frequency, ted err is the filtered timing error detector output and f mclk / 2 25 is the nco resolution. for example, to set the symbol frequency to 1.64mhz the symfreq register must be loaded with the value 00231a8b (hex) equivalent to 2300555 (dec). timing error detector the timing error detector (ted) is based on a one sample per symbol algorithm to compute the timing error between the demodulated symbol at the matched filter output and the optimum sampling instant. the output of the detector is given by the following equation: ted err = i n x sgn(i n-1 ) - i n-1 x sgn(i n ) + q n x sgn(q n-1 ) - q n-1 x sgn(q n ) this signal is filtered by the timing loop filter and then sent to the timing nco to close the tracking loop. the ted gain (k d ) characteristic as a function of the carrier to noise ratio is given in fig.11. k d = 0.56 is the value for a noise free input signal and may be reduce up to 40% of its maximum value in a low c/n condition. df dt ------- 2 swstep stepper 1 + ---------------------------------------- f mclk 2 2 28 ------------------ [hz/s] =
19/117 STA400A figure 11. timing error detector gain timing loop filter the timing loop filter is a first order iir filter with two programmable parameters, one for the proportional and the other for the integral correction, as shown in fig.6. the output of the integrator, that produces a frequency control term, is summed with the weighted timing error in the proportional path and then sent to the timing nco to close the timing tracking loop. the proportional gain alpha and the integral gain beta of the filter are programmable by the registers alfatim and betatim respectively. the integral gain is set by a mantissa and exponent as given by: beta = beta_m x 2 (beta_e) where beta_m, the mantissa, is a 5-bit integer value set in the five lsbs of the betatim register (beta_m=be- tatim[4:0]) and beta_e, the exponent, is a 3-bit integer set in the three msbs of the betatim register (beta_e=betatim[7:5]). the proportional gain is an integer value set in the alfatim register with a range from 0 to 255 (alpha=alfa- tim[7:0]). the timintg register collects the 8 msbs of the filter integrator and may be read or written at any time by the system controller. when the register is written the integrator lsbs are reset. a limiter is provided on the filter integrator to limit the frequency sweep of the timing nco. after a drop-out or during the unlock condition, the frequency uncertainty of the timing nco (that produces a symbol slip on the demodulated data) can be controlled setting the maximum number of bit in the timing integrator. this value is set in the limiter block by the timlpf_length parameter (see timlpf_ctrl register). the limiter peak- to-peak range can take 8 values from 8-bits to 20-bits corresponding to a frequency shift from 182hz to 7.5khz respectively. timing integrator control this block operates on the timing loop integrator. during a very long drop-out or when no signal is applied to the demodulator input, the timing loop integrator may drift up to the saturation value. as the signal is applied again or after the drop-out event, it is possible that the integrator remains in saturation for a long period causing a very slow symbol re-acquisition time. the timintgctrl block recognizes this event and sends a reset to the integrator register to speed-up the re-acquisition phase. the flow diagram of the timintgctrl block finite state machine (fsm) is depicted in fig.12. the fsm parameters and the block enable/disable command are set in the timlpf_ctrl register 0 2 4 6 8 10 12 14 16 18 20 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 ted gain c/n (db)
STA400A 20/117 figure 12. timingctrl fsm flow diagram timing loop equations the timing recovery is fully digital and comprises two blocks working at symbol rate: the timing error detector and the loop filter and two blocks working at clock rate: the timing nco and the nyquist/interpolator filters (see fig.6). the loop is parametrised by the coefficients alpha and beta given in the registers alfatim and betatim re- spectively. the timing loop is a second order loop whose natural frequency f n and damping factor x may be cal- culated by the following formulas: where alpha is set in the alfatim register and beta in the betatim register, k d is the ted gain as shown in fig.11 and m is the reference level of the agc2 loop (see agc2ref register). for example, to set the loop natural frequency to 126hz with the default value for m=agc2ref (90dec, 5ahex) and k d = 0.56 (noise free value), the above equation solved for beta gives: alpha can be chosen to have a damping factor equal to 0.7: the register alfacar can be programmed with 5 (dec) and the register betacar can be programmed with the parameter beta_e=0 and beta_m=14 (dec). demodulator unlocked (lock=1) demodulator locked (lock=0) demodulator unlocked for a time less than a fixed value (timintg_clr_win) demodulator unlocked demodulator unlocked for a time equal to a fixed value (timintg_clr_win) reset time counter clear releasing in the time loop filter integrator time counter active time counter reset time loop filter integrator cleared demodulator locked (lock=0) or timing_clr_en=0 f n 4.76 mk d beta [hz] z 0.075 alpha mk d beta ------------ - == beta f n 2 22.6576mk d ---------------------------------- 13.90 == alpha z 0.075 -------------- - beta mk d ------------ - 4.9 ==
21/117 STA400A c/n estimator this block gives the signal to noise ratio at the nyquist filter output. it computes the statistic (mean and variance) of a single component of the demodulated complex signal and writes the estimated c/n value in db in the cn register. this register has a fixed point format. the integer part of the number is stored in the six msbs (bit7-2) and the fractional part in the two lsbs (bit1-0). the c/n estimation is correct only when the qpsk demodulator is locked. carrier null offset this block is used to enhance the acquisition performance of the carrier loop. it may be enabled/disabled setting bit-6 of the qpsk_ctrl register. the block consists of a fsm that is activated when the carrier loop has reached the lock condition (low level on at the lock detector output). the fsm checks if the lock detector output is low for a programmable period (see nulofs_win register) and then it writes the locked carrier frequency value (read from the carfreq register) into the carrier nco. it resets also the carrier loop filter integrator and disables the frequency sweep (see fig.6). in this way the demodulator works with a null carrier offset resulting in a faster re-acquisition time of the carrier in case of a signal drop-out. the nulofs_deltaf register gives the possibility to subtract a programmed fre- quency from the locked carrier before writing the new value in the carrier nco. the flow diagram of the carriernulloffset fsm is showed in fig.13 flag register a flag register is provided in the qpsk demodulator. this is a read only register containing specific status bits of the demodulator. it gives information on the lock staus and on the operation of the carriernulloffset and ti- mintgctrl blocks. figure 13. carriernulloffset fsm flow diagram demodulator locked (lock=0) demodulator unlocked system reset or block disable demodulator locked for a time less than a fixed value (nulofs_win) demodulator locked for a time equal to the fixed value (nulofs_win) no system reset and block enable reading lock reading lock time counter active frequency.sweep disabled carrier loop filte integrator cleared writing new if frequency in the carrier nco: new_if_freq= carfreq-nulofs_deltaf clear release in the carrier loop filter integrator system reset or block disable (nulofs_en=0) or demodulator unlocked (lock=1)
STA400A 22/117 1.3 terrestrial demodulation (to be completed) the multicarrier modulated (mcm) terrestrial signal is sampled at 23.92 mhz and converted to 10-bit. the ter- restrial demodulator processes these samples at four time the mcm symbol rate (4*2.99 mhz = 11.96 mhz) and includes the final down-convertion and i/q symbol generation, low-pass filtering and down-sampling to mcm symbol rate (2.99 mhz). the mcm demodulation is performed by an fft over 768 samples. the multicarrier demodulator also includes frequency and symbol synchronization, amplitude-modulated synchronisation sym- bol (amss) detection for frame synchronisation, guard interval removal, differential decoding, demapping and metric generation. all the mcm demodulator functionality are programmable by the microcontroller; the register map is listed in sections 2.3 and 2.9. 1.4 tdm decoding (to be completed) there are two different tdm structures within the dars system, the satellite tdm and the terrestrial tdm, car- rying the same payload channels (pc), which are included in a 432 msec framed packet consisting of one or more prime rate channel (prc) with reed-solomon protection (outer encoding). the combined satellite transmission includes a punctured rate 3/8 convolutional inner encoder (from a mother code of rate 1/3 and "1 out of 9" punctured scheme) and a convolutional interleaved with 4.698 sec. delay. each satellite transports one half of the punctured and interleaved pc resulting in an effective inner encoder rate of 3/4. up to 256 prcs are multiplexed together into a time division multiplex (tdm) structure. the time slot control channel (tscc), containing information of the tdm structure, is added at the begin of the fully fec protected pcs. after the insertion of 1 master frame preamble (mfp), 205 fast synchronization preamble (fsp) and the padding field (pad) the complete satellite master frame (mf) contains 1416960 bits over 432 msec, resulting in a satellite tdm bit-rate of 3.28 mbits/sec. the terrestrial bit-stream is a repeater signal from the satellite transmission. the inner encoder has a convolu- tional code rate of 3/5 (from a mother code of rate 1/3 and "4 out of 9" punctured scheme) and does not include convolutional interleaving. the terrestrial mf structure contains only 3 fields: mfp, data field (tscc/pcs) and pad resulting in a 1755360 bits over 432 msec. for a bit-rate of 4.063333 mbits/sec. the tdm decoder receives the demodulated symbol streams from the two satellite and the terrestrial demodu- lators. the tdm processing includes sat-sat combining, frame synchronization, external memory management and prc demultiplexing. the frame synchronization is based on the mfp detection. the mfp and fsp are also used for the phase am- biguity resolution of the satellite demodulated data and for fast synchronization after a short dropout and cycle- slip. the prc demultiplexer processes the tscw (time slot control word) from the tscc field to extract all the information needed for the allocation of the prcs to the selected pcs. up to 50 prcs (48 prcs plus 2 tscc) can be demultiplexed resulting in a maximum pc bit stream rate of 414.8 kbit/s (384kbit/s of useful data). the programmable register for the tdm decoding are explained in sections 2.4 and 2.8. 1.5 fec (to be completed) the prc and the tscc data from the external memory are decoded by the fec (viterbi decoder, reed-so- lomon decoder and block deinterleaver) and sent to the pc-bitstream interface. the prc-based packet structure of the service layer and the external memory allow the use of one viterbi de- coder and one rs decoder for both the combined-satellite and terrestrial tdm frame. the first operation of the fec block is a data pre-processing for buffering, reordering and demultiplexing of the data streams coming from the external memory and containing both the satellite and terrestrial tdm. in this phase the depuncturing process is also performed.
23/117 STA400A the depunctured r=1/3 coded data stream (equal for combined-satellite and terrestrial) is decoded by the vit- erbi decoder using 6 bit of quantization (1 hard bit and 5 soft bits). the outer decoding process, the block deinterleaving and the satellite/terrestrial selective combining is performed by the rs decoder circuit. additional feature of the fec block is the bit error rate estimation (computed separately for terrestrial and combined sat- ellite) based on the re-encoding of the viterbi decoded bit-stream. 1.6 pc bitstream interfaces after demodulation, tdm processing and fec decoding the cdec delivers the tscc and the selected prcs to external devices for further processing. to implement this function, STA400A contains two identical payload channel (pc) bitstream interfaces (see fig.1). each pc interface performs the parallel to serial conversion and the reformatting of the data packets coming from the prc demux control block and provides serial data, clock and synchronization signals to the pc output ports. the payload channel output protocol (showed in fig.14) is configurable, independently for the two interfaces, via the pc interface registers described in section 2.7. figure 14. pc bitstream output protocol the 432ms tdm frame is divided in 50 time intervals with the first two containing the tscc data. each time interval contains a burst of 448 bytes (2 header bytes h1 and h2, and 446 bytes of prc data) transmitted from the prc demux to the pc interface. the pc output ports are enabled depending on the settings of the register pcid data wr (addr: 0x0651-0x0652). each output port provides 5 signals: n pcsd, payload channel serial data n pcdc, payload channel data clock n pcfs, payload channel prc frame sync n pcbs, payload channel byte sync pcsd pcdc pcfs 432ms frame period clock tscc1 tscc2 prc_an prc_a1 prc_b1 prc_zn prc_z1 prc_bn pcsd pcdc pcfs h1 h2
STA400A 24/117 n pcts_ef, payload channel tscc sync / reed-solomon error flag the pcdc frequency can be set from 11.96 mhz to 373.75 khz via the 5 msbs of the pcdc_conf register (pcdc_conf[6:2]); the clock polarity and the clock configuration (always running or fixed to '1' when the inter- face is not transmitting data) can be configured via the pcdc_conf[1] and the pcdc_conf[0] bits respec- tively. the pcsd data format can be set via the pcsd_conf register; pcsd_conf[0] and pcsd_conf[1] define if data are transmitted msb or lsb first and if a parity bit is appended or not to each data byte respectively the calculated parity can be even or odd depending on the content of pcsd_conf[2] bit. pcfs is the prc packet synchronization; the default setting is one pulse at the beginning of each burst of 448 bytes. pcbs is a byte synchronization signal with one pulse at the beginning of each decoded data byte (de- fault configuration). pcts_ef can be configured as the tscc synchronization signal (default configuration) or as the reed-so- lomon error flag signal. the tscc synchronization is a pulsed signal having period t=432ms (one pulse every tdm frame). the width of the synchronization pulses is equal to 1 pcdc cycle. the parameters of these last three signals can be configured via the pcsync_conf register. 1.7 micropocessor interface data communication between the microcontroller and the device takes place through the 2 wires (sda and scl) iic-bus interface. the STA400A is always a slave device. the STA400A register map is organized in 8 main pages with a base address given in table 2.2. after the de- vice address, to read or write a register, the microcontroller must send first the base-address to select one of the 8 pages and a relative-address to select the register inside the page. the STA400A has byte or multibytes registers access with different classes (see table 2.1); the complete list of the registers is given in the register map section. interrupt line the interrupt line of the STA400A (pin 53 - intr) or-wires 8 different interrupt requests from the cdec that can be individually masked by the registers irq1_mask (address 0x0417). the interrupt vector is represented by the irq1_status register (address 0x0419) described in section 2.6. after an interrupt request, the intr pin remains at high level, except for the mfp_clk interrupt bit5, that is an impulse periodic signal. the irq1_status interrupt vector may be automatically reset after the read operation or may be reset by the microcontroller (writing 0x00) depending on the bit0 of the control register (see sec- tion 2.6) iic-bus specification the i2c-bus protocol defines any device that sends data on to the bus as a transmitter and any device that reads the data as a receiver. the device that controls the data transfer is known as the master and the others as the slave. the master will always initiate the transfer and will provide the serial clock for synchronisation. data transition or change data changes on the sda line must only occur when the scl clock is low. sda transitions while the clock is high are used to identify start or stop condition. start condition start is identified by a high to low transition of the data bus sda signal while the clock signal scl is
25/117 STA400A stable in the high state. a start condition must precede any command for data transfer. stop condition stop is identified by low to high transition of the data bus sda signal while the clock signal scl is stable in the high state. a stop condition terminates communications between STA400A and the bus master. acknowledge bit an acknowledge bit is used to indicate a successful data transfer. the bus transmitter, either master or slave, will release the sda bus after sending 8 bits of data. during the 9th clock pulse the receiver pulls the sda bus low to acknowledge the receipt of 8 bits of data. some registers do not give acknowledge when the data is not available. data input during the data input the STA400A samples the sda signal on the rising edge of the clock scl. for cor- rect device operation the sda signal has to be stable during the rising edge of the clock and the data can change only when the scl line is low. device addressing to start communication between the master and the STA400A, the master must initiate with a start con- dition. following this, the master sends onto the sda line 8 bits (msb first) corresponding to the device select address and read or write mode. the 7 most significant bits are the device address identifier, corresponding to the i2c bus definition. for the STA400A these are fixed as 1101010. the 8th bit (lsb) is the read or write operation bit (rw; set to 1 in read mode and to 0 in write mode). after a start condition the STA400A identifies on the bus the device address and, if matched, it will acknowledges the identification on sda bus during the 9th bit time. the following 2 bytes after the device identification byte are the internal space address. write operation (see fig. 15) following a start condition the master sends a device select code with the rw bit set to 0. the STA400A gives the acknowledge and waits for the 2 bytes of internal address. the least significant 15 bits of the 2 bytes address provides access to any of the internal registers. the most significant bit means incremental mode (1 = auto incremental enabled, 0 = auto incremental disabled). the STA400A has an internal byte address counter. each time a byte is written or read, this counter, ac- cording to the autoincremental bit setting, is incremented or not. after the reception of each of the internal bytes address the STA400A again responds with an acknowl- edge. byte write in the byte write mode the master sends one data byte and this is acknowledged by STA400A. the mas- ter then terminates the transfer by generating a stop condition. the multibyte write needs the auto in- cremental mode bit set to '1'. multibyte write the multibyte write mode can start from any internal address. the master sends the data and each one is acknowledged by the STA400A. the transfer is terminated by the master generating a stop condition.
STA400A 26/117 read operation (see fig. 16) current byte address read for the current byte address read mode, following a start condition the master sends the device ad- dress with the rw bit set to 1. the STA400A acknowledges this and outputs the byte addressed by the internal byte address counter. the counter is then incremented or not depending on the auto incremental bit. the master does not ac- knowledge the received byte, but terminates the transfer with a stop condition. random byte address read a dummy write is performed to load the byte address into the internal address counter. this is followed by another start condition from the master and the device address repeated with the rw bit set to 1. the STA400A acknowledges this and outputs the byte addressed by the internal byte address counter already loaded the master does not acknowledge the received byte, but terminates the transfer with a stop condition. sequential address read this mode can be initiated with either a current address read or a random address read. however in this case the master does acknowledge the data byte output and the STA400A continues to output the next byte in sequence, providing that the auto incremental mode bit be set. to terminate the stream of bytes the master does not acknowledge the last received byte, but terminates the transfer with a stop condition. the output data stream is from consecutive byte addresses, with the internal byte address counter auto- matically incremented after each byte output. figure 15. write mode sequence figure 16. read mode sequence dev ack start d97au669 rw byte ack byte ack data in ack stop byte write dev ack start rw byte ack byte ack data in ack stop multibyt write data in ack dev ack start d97au670 rw data no ack stop current address read dev ack start rw byte ack byte ack dev ack stop random address read data no ack start rw dev ack start data ack data ack stop sequential current read data no ack dev ack start rw byte ack byte ack dev ack sequential random read data ack start rw data ack no ack stop data rw= high
27/117 STA400A 2register map table 1. register classes pr: event counter. (increments if input =1 and will be reset after read access to preset value) pri: event counter like pr-register, plus trigger output signal if maximum is arrived. wrt: write and read register plus trigger output signal when write access. rt: read only register plus trigger output signal when read access. int: this register class always consists out of a status and mask register. the status register stores interrupt signals from cdec. the mask registers determines if an interrupt signal should generate an irq_out signal or not. trt: a transparent register does not exists physically in the register map. the register map pipelines the information to the cdec register. the register operates as a normal write/read register in the register map. note: the pr and rt register classes must be read with the random address read mode only. sequential read mode is not allowed. table 2. base address list abbreviations name of register class wr write and read r read rt read plus en-trigger pr preset when read pri preset when read plus trigger signal wrt write and read plus trigger signal int interrupt register pair trt transparent base address (hex) block 00 satellite demodulators (satdem1 + satdem2) 01 terrestrial demodulator (section 1) 02 tdm (section 1) 03 fec 04 if sampling and control interface 05 pc bitstream interface 06 tdm (section 2) 07 terrestrial demodulator (section 2)
STA400A 28/117 2.1 register map overview table 3. qpsk demodulator #1 (s1-early) base address: 00 - address range: 59 - 77 relative address (hex) register name wl type reset value (hex) comment 59 qpsk_demod_en 1 wr 01 qpsk dem enable register 5a qpsk_ctrl 8 wr 47 qpsk dem control register 5b pfdthr 6 wr 14 phase/freq. detector threshold 5c symfreq0 8 wr 8b symbol frequency (lsb) 5d symfreq1 8 wr 1a 5e symfreq2 8 wr 23 5f symfreq3 1 wr 00 symbol frequency (msb) 60 iffreq0 8 wr ec intermediate frequency (lsb) 61 iffreq1 8 wr c4 62 iffreq2 8 wr 4e 63 iffreq3 4 wr fb intermediate frequency (msb) 64 alfacar 8 wr 17 carrier loop filter alpha param. 65 betacar 8 wr 15 carrier loop filter beta param. 66 alfatim 8 wr 07 timing loop filter alpha param. 67 betatim 8 wr 0e timing loop filter beta param. 68 rampctrl 7 wr 20 ramp control register 69 agc2beta 3 wr 03 agc2 gain 6a agc2ref 8 wr 5a agc2 reference 6b agc2intg 8 wr 00 8msb of agc2 loop integrator 6c timintg 8 wr 00 8msb of timing loop integrator 6d carintg 8 wr 00 8msb of carrier loop integrator 6e carfreq0 8 r -- locked carrier frequency (lsb) 6f carfreq1 8 r -- 70 carfreq2 8 r -- 71 carfreq3 4 r -- locked carrier frequency (msb) 72 cn 8 r -- c/n esteem 73 flag 4 r -- demodulator status 74 nulofs_win 4 wr 07 null carrier offset window 75 nulofs_deltaf 8 wr 2b null carrier offset delta frequency 76 timlpf_ctrl 8 wr 90 timing loop low pass filter control 77 lockthr 2 wr 02 lock detector threshold
29/117 STA400A table 4. qpsk demodulator #2 (s1-late) base address: 00 - address range: 7f - 9d relative address (hex) register name wl type reset value (hex) comment 7f qpsk_demod_en 1 wr 01 qpsk dem enable register 80 qpsk_ctrl 8 wr 47 qpsk dem control register 81 pfdthr 6 wr 14 phase/freq. detector threshold 82 symfreq0 8 wr 8b symbol frequency (lsb) 83 symfreq1 8 wr 1a 84 symfreq2 8 wr 23 85 symfreq3 1 wr 00 symbol frequency (msb) 86 iffreq0 8 wr 9e intermediate frequency (lsb) 87 iffreq1 8 wr d8 88 iffreq2 8 wr 89 89 iffreq3 4 wr fc intermediate frequency (msb) 8a alfacar 8 wr 17 carrier loop filter alpha param. 8b betacar 8 wr 15 carrier loop filter beta param. 8c alfatim 8 wr 07 timing loop filter alpha param. 8d betatim 8 wr 0e timing loop filter beta param. 8e rampctrl 7 wr 20 ramp control register 8f agc2beta 3 wr 03 agc2 gain 90 agc2ref 8 wr 5a agc2 reference 91 agc2intg 8 wr 00 8msb of agc2 loop integrator 92 timintg 8 wr 00 8msb of timing loop integrator 93 carintg 8 wr 00 8msb of carrier loop integrator 94 carfreq0 8 r -- locked carrier frequency (lsb) 95 carfreq1 8 r -- 96 carfreq2 8 r -- 97 carfreq3 4 r -- locked carrier frequency (msb) 98 cn 8 r -- c/n esteem 99 flag 4 r -- demodulator status 9a nulofs_win 4 wr 07 null carrier offset window 9b nulofs_deltaf 8 wr 2b null carrier offset delta frequency 9c timlpf_ctrl 8 wr 90 timing loop low pass filter control 9d lockthr 2 wr 02 lock detector threshold
STA400A 30/117 table 5. terrestrial demodulator (section 1 ) base address: 01 - address range: 00 - c1 relative address (hex) register name wl type reset value (hex) comment 00 enable_m 8 wr ff enable signals for mcm submodules 01 status1_m 8 r 00 status information of mcm submodules 02 status2_m 2 r 00 04 dataovf_m 8 pr 00 overflow event counter of mcm submodules 06 iqgmode_m 3 wr 02 iq generation mode 07 clk_devcomp_m 1 wr 01 selects mode of clk deviation compensation 08 amssthrl_m 7 wr 37 low threshold of amss detection 09 amssthrh_m 7 wr 41 high threshold of amss detection 0a amssfailed_m 3 wr 07 if not more than mrm_sync_min_amss_failed amss-not-detected events : pre-sync -> hunt 0b syncsearch_m 4 wr 0a number of mcm-frames during pre sync state 0c syncloss1_m 8 wr ff number of allowed amss failed events (sync -> hunt) 0d syncloss2_m 3 wr 03 0e framelen_m 8 wr b4 frame window length of amss detection 0f channellen_m 8 wr b4 channel window length of amss detection 10 cyclecnt1_m 8 r -- actual difference of mcm-frame cycle count to nominal value. 11 cyclecnt2_m 4 r -- 12 cyclecntref1_m 8 wrt 00 external setting of actual difference of mcm-frame cycle count to nominal value 13 cyclecntref2_m 4 wrt 00 15 attfactor1_m 8 wr f0 attenuation factor for correlation results. 16 attfactor2_m 5 wr 1f 17 histlen_m 4 wr 0f length of history register 19 cn1_m 8 r -- estimated noise and signal&noise power. 1a cn2_m 8 r -- 1b cn3_m 8 r -- 1c ffctrl_m 6 wr 1e control of ff internal algorithm 1d ffbeta_m 8 wr 04 loop filter constant beta 1f blkdetect_m 1 wr 00 external setting of blockage condition to fc 20 initdelay_m 2 wr 00 delay on use of ff output at startup 21 maxfreq1_m 8 wr 46 maximum allowed difference of ff and cf to detect out-of-range condition of ff. 22 maxfreq2_m 5 wr 00 23 mincf_m 8 wr 90 confidence value for cf estimation
31/117 STA400A relative address (hex) register name wl type reset value (hex) comment 24 cfref1_m 8 wrt 00 external setting of cf offset value. 25 cfref2_m 5 wrt 00 26 cfvalue1_m 8 r -- actual cf offset value. 27 cfvalue2_m 5 r -- 28 ffscale_m 8 wr e0 scale factor multiplied with ff value 2a ff_oor_m 8 pr 00 counter for ff_out_of_range events 33 epocen_m 1 wr 01 epoc enable 34 demapctrl_m 8 wr e0 control of demapping 35 epocthr1_m 8 wr 00 control of epoc algorithm 36 epocthr2_m 6 wr 06 37 normshift_m 4 wr 0b normalization shift for fft data 38 linscale_m 8 wr 80 a linear scaling of the fft output data 39 shiftovfl_m 8 pr 00 overflow counter if norm shift 0x37 is too large 3b limitovfl_m 8 pr 00 overflow counter if input data for pp exeeds input range 3c epoccarriers1_m 8 r -- number of carriers used for epoc correction in current mcm symbol 3d epoccarriers2_m 2 r -- 3e epocrotre_m 8 r -- epoc correction phasor (real part) 3f epocrotim_m 8 r -- epoc correction phasor (imag part) 40 psframecnt_m 4 r -- counter of frames during presync state 41 ps_noamsscnt_m 3 r -- counter of frames without amss detection 42 amssfailcnt1_m 8 r -- counter of sequent frames without amss detection. 43 amssfailcnt2_m 8 r -- 44 oivlamssfail1_m 8 r -- number of failed amss dectection during an interval set by register 0x0195/96. 45 oivlamssfail2_m 4 r -- 47 maxcorriw_m 7 rt -- maximum correlation inside channel window 49 maxcorrow_m 7 rt -- maximum correlation outside channel window 4b mincorriw_m 7 rt -- minimum correlation inside channel window 4d mincorrow_m 7 rt -- minimum correlation outside channel window 4f frametoggle_m 1 r -- with each mcm frame register value changes between 0 and 1 50 corrmaxakt_m 7 r -- stores the current weighted maximum correlation value inside channel window 51 corrmaxpos1_m 8 r -- stores the current position inside frame window. table 5. terrestrial demodulator (section 1 ) (continued)
STA400A 32/117 relative address (hex) register name wl type reset value (hex) comment 52 corrmaxpos2_m 3 r -- 53 posshift1_m 8 r -- real shift operation after checking history. 54 posshift2_m 4 r -- 55 winjump1_m 8 r -- real jump of window. 56 winjump2 3 r -- 60 ncoinc1_m 8 r -- nco increment. 61 ncoinc2_m 8 r -- 62 ncoinc3_m 1 r -- 70 ffest1_m 8 r -- actual fine frequency value. 71 ffest2_m 8 r -- 72 ffest3_m 1 r -- 80 mctlen_m 1 wr 00 mcm control 81 mctlmask_m 6 wr 1f mcm control masks 82 mctlinit_m 1 wrt 00 mcm control initialization trigger 83 tdmcntth_m 8 wr 18 number of tdm frames in lock for transition to state no_update 84 mctlstate_m 2 r 00 mcm control status 90 meanabs_m 8 r 00 mean of absolute value of mcm output symbols 91 cliprate_m 8 r 00 mcm output clip rate 95 oivllenamssfail1_m 8 wr 8b sets length of observation interval of reg 0x0144/45 (139 frames =~ 1 sec). 96 oivllenamssfail2_m 4 wr 0f 97 winjplimit1_m 8 wr 03 sets maximal allowed jump of window. 98 winjplimit2_m 3 wr 00 9a jplimitevt_m 8 pr 00 counts jump limit events 9b winjpnolimit1_m 8 wr 00 actual requested jump of window without limit function. 9c winjpnolimit2_m 3 wr 00 b0 iqgdataovf_m 8 pr 00 overflow event counter of lpf inside iqgen b2 ncodataovf_m 8 pr 00 overflow event counter of nco b4 lpfdataovf_m 8 pr 00 overflow event counter of lpf c0 irqmask_m 2 int 00 mcm interrupt mask c1 irqstatus_m 2 int 00 mcm interrupt status table 5. terrestrial demodulator (section 1 ) (continued)
33/117 STA400A table 6. tdm (section 1) base address: 02 - address range: 00 - cb relative address (hex) register name wl type reset value (hex) comment 00 tdmenable_s 8 wr ff satellite tdm decoding block enable 04 tdmsync_s1 5 wr 10 satellite one tdm decoding synchronization data control 05 mfplength_s1 4 wr 0f satellite one tdm decoding extended mfp detection window length 06 mfpthr_s1 7 wr 44 satellite one tdm decoding extended mfp detection threshold 07 synclength_s1 4 wr 03 satellite one tdm decoding synchronization window length 08 presyncthr_s1 4 wr 02 satellite one tdm decoding pre-synchronization lost threshold 09 syncthr_s1 4 wr 0b satellite one tdm decoding synchronization lost threshold 0a fspthr_s1 6 wr 14 satellite one tdm decoding fsp invalid threshold 0b metricctrl_s1 4 wr 00 satellite one tdm decoding qpsk metric generation data control 0c scrambler1_s1 8 wr 05 satellite one tdm decoding scrambler polynomial 0d scrambler2_s1 4 wr 08 12 tdmsync_s2 5 wr 10 satellite one tdm decoding synchronization data control 13 mfplength_s2 4 wr 0f satellite two tdm decoding extended mfp detection window length 14 mfpthr_s2 7 wr 44 satellite two tdm decoding extended mfp detection threshold 15 synclength_s2 4 wr 03 satellite two tdm decoding synchronization window length 16 presyncthr_s2 4 wr 02 satellite two tdm decoding pre-synchronization lost threshold 17 syncthr_s2 4 wr 0b satellite two tdm decoding synchronization lost threshold 18 fspthr_s2 6 wr 14 satellite two tdm decoding fsp invalid threshold 19 metricctrl_s2 4 wr 00 satellite two tdm decoding qpsk metric generation data control 1a scrambler1_s2 8 wr 05 satellite two tdm decoding scrambler polynomial 1b scrambler2_s2 4 wr 08 1d mfplock_s1 7 r -- satellite two tdm decoding status 1e mfplost_s1 4 r -- satellite one tdm decoding extended mfp counter 20 mfpw_re_s1 8 r -- satellite one tdm decoding extended mfp correlation weight, real part 21 mfpw_im_s1 8 r -- satellite one tdm decoding extended mfp correlation weight, imaginary part 22 fspw_re_s1 7 r -- satellite one tdm decoding fsp correlation weight, real part
STA400A 34/117 relative address (hex) register name wl type reset value (hex) comment 23 fspw_im_s1 7 r -- satellite one tdm decoding fsp correlation weight, imaginary part 24 fspphase_s1 2 r -- satellite one tdm decoding phase 25 mfplock_s2 7 r -- satellite two tdm decoding status 26 mfplost_s2 4 r -- satellite two tdm decoding extended mfp counter 28 mfpw_re_s2 8 r -- satellite two tdm decoding extended mfp correlation weight, real part 29 mfpw_im_s2 8 r -- satellite two tdm decoding extended mfp correlation weight, imaginary part 2a fspw_re_s2 7 r -- satellite two tdm decoding fsp correlation weight, real part 2b fspw_im_s2 7 r -- satellite two tdm decoding fsp correlation weight, imaginary part 2c fspphase_s2 2 r -- satellite two tdm decoding phase 2d tdmenable_t 5 wr 1f terrestrial tdm decoding block enable 2e mfplength_t 4 wr 07 terrestrial tdm decoding mfp detection window length 2f mfpthrpresync_t 7 wr 2c terrestrial tdm decoding mfp detection threshold, pre-synchronization 30 mfpthrsync_t 7 wr 28 terrestrial tdm decoding mfp detection threshold, synchronization 31 synclength_t 5 wr 03 terrestrial tdm decoding tdm synchronization window length 32 syncthr_t 4 wr 02 terrestrial tdm decoding tdm synchronization found threshold 33 synclost_t 4 wr 0b terrestrial tdm decoding tdm synchronization lost threshold 34 scrambler1_t 8 wr 05 terrestrial tdm decoding scrambling polynomial 35 scrambler2_t 4 wr 08 36 dataformat_t 4 wr 00 terrestrial tdm decoding data formatting 37 tdmstatus_t 3 r -- terrestrial tdm decoding status 39 mfplost_t 4 r -- terrestrial tdm decoding mfp correlation lost 3a mfpw_re_t 8 r -- terrestrial tdm decoding mfp correlation weight, real part 3b mfpw_im_t 8 r -- terrestrial tdm decoding mfp correlation weight, imaginary part 3c tdmphase_t 2 r -- terrestrial tdm decoding tdm phase 3f tdmsyncctrl_t 1 wr 01 terrestrial tdm decoding synchronization control 40 swfgenable_s 8 wr ff satellite weighting factor generation block enable 41 swfgstatus_s 2 r -- satellite weighting factor generation status 50 prc_en 3 wr 00 0: tdm prc interface block enable; 2:1 tdm prc interface prc source table 6. tdm (section 1) (continued)
35/117 STA400A relative address (hex) register name wl type reset value (hex) comment 51 prc_num1 8 wr 00 tdm prc interface: prc number. (range from 1 to 258). 52 prc_num2 1 wr 00 60 descdataen 5 wr 00 select signal for multiplexers after descrambler 61 descdata_re_t 8 wr 00 real terrestrial test data 62 descdata_im_t 8 wr 00 imag terrestrial test data 63 descdata_re_s1 4 wr 00 real satellite one test data 64 descdata_im_s1 4 wr 00 imag satellite one test data 65 descdata_re_s2 4 wr 00 real satellite two test data 66 descdata_im_s2 4 wr 00 imag satellite two test data 67 descdata_s1wfg 4 wr 00 swfg one test data 68 descdata_s2wfg 4 wr 00 swfg two test data 80 tpmenable_s 2 wr 00 satellite tdm preamble monitor block enable 81 tpmdataformat_s1 2 wr 00 satellite one tdm preamble monitor input data format 82 tpmmfpthr_s1 7 wr 28 satellite one tdm preamble monitor mfp detection threshold 83 tpmfspthr_s1 6 wr 14 satellite one tdm preamble monitor fsp detection threshold 84 tpmdataformat_s2 2 wr 00 satellite two tdm preamble monitor input data format 85 tpmmfpthr_s2 7 wr 28 satellite two tdm preamble monitor mfp detection threshold 86 tpmfspthr_s2 6 wr 14 satellite two tdm preamble monitor fsp detection threshold 90 tpmmfpw_re_s1 8 r -- satellite one tdm preamble monitor mfp correlation weight, real part 91 tpmmfpw_im_s1 8 r -- satellite one tdm preamble monitor mfp correlation weight, imaginary part 92 tpmmfpsymslip1_s1 8 r -- satellite one tdm preamble monitor mfp symbol slip 93 tpmmfpsymslip2_s1 4 r -- 94 tpmfspw_re_s1 7 r -- satellite one tdm preamble monitor fsp correlation weight, real part 95 tpmfspw_im_s1 7 r -- satellite one tdm preamble monitor fsp correlation weight, imaginary part 96 tpmfspposslip1_s1 8 r -- satellite one tdm preamble monitor fsp position slip 97 tpmfspposslip2_s1 4 r -- 98 tpmfsptdmphase_s1 2 r -- satellite one tdm preamble monitor fsp phase 99 tpmprdetect_s1 2 r -- satellite one tdm preamble monitor preamble detection 9a tpmfspcyslipcnt_s1 8 r -- satellite one tdm preamble monitor fsp cycle slip counter table 6. tdm (section 1) (continued)
STA400A 36/117 relative address (hex) register name wl type reset value (hex) comment 9b tpmfspposlipcnt_s1 8 r -- satellite one tdm preamble monitor fsp position slip counter a0 tpmmfpw_re_s2 8 r -- satellite two tdm preamble monitor mfp correlation weight, real part a1 tpmmfpw_im_s2 8 r -- satellite two tdm preamble monitor mfp correlation weight, imaginary part a2 tpmmfpsymslip1_s2 8 r -- satellite two tdm preamble monitor mfp symbol slip a3 tpmmfpsymslip2_s2 4 r -- a4 tpmfspw_re_s2 7 r -- satellite two tdm preamble monitor fsp correlation weight, real part a5 tpmfspw_im_s2 7 r -- satellite two tdm preamble monitor fsp correlation weight, imaginary part a6 tpmfspposslip1_s2 8 r -- satellite two tdm preamble monitor fsp symbol slip a7 tpmfspposslip2_s2 4 r -- a8 tpmfsptdmphase_s2 2 r -- satellite two tdm preamble monitor fsp phase a9 tpmprdetect_s2 2 r -- satellite two tdm preamble monitor preamble detection aa tpmfspcyslipcnt_s2 8 r -- satellite two tdm preamble monitor fsp cycle slip counter ab tpmfspposlipcnt_s2 8 r -- satellite two tdm preamble monitor fsp position slip counter b0 tdmsyslip1_s1 8 r -- satellite one tdm decoding symbol slip b1 tdmsyslip2_s1 4 r -- b2 tdmsyslip1_s2 8 r -- satellite two tdm decoding symbol slip b3 tdmsyslip2_s2 4 r -- b4 tdmsyslip1_t 8 r -- terrestrial tdm decoding symbol slip b5 tdmsyslip2_t 2 r -- c0 fspstarwinlen_s1 3 wr 02 satellite one tdm decoding fsp detection start window length c1 fsphuntwininc_s1 4 wr 03 satellite one tdm decoding fsp detection hunt window increment c2 fspshdropoutlen_s1 5wr 0f satellite one tdm decoding fsp short dropout length c3 fspsecualignthr_s1 3 wr 03 satellite one tdm decoding fsp secure alignment threshold c8 fspstarwinlen_s2 3 wr 02 satellite two tdm decoding fsp detection start window length c9 fsphuntwininc_s2 4 wr 03 satellite two tdm decoding fsp detection hunt window increment ca fspshdropoutlen_s2 5wr 0f satellite two tdm decoding fsp short dropout length cb fspsecualignthr_s2 3 wr 03 satellite two tdm decoding fsp secure alignment threshold table 6. tdm (section 1) (continued)
37/117 STA400A table 7. fec base address: 03 - address range: 00 - 51 relative address (hex) register name wl type reset value (hex) comment 00 control_f 6 wr 3f control vector for fec and fec preprocessing 01 status_f 4 r -- status flags of fec processing blocks (fec preproc, vd, fec mgmt, rs input control) 02 errorctrl_f 6 wr 01 fec error reporting 07 initstate_f 6 wr 2e initial state of convolutional decoder after training sequence 08 initlfsr1_f 8 wr cc initial state of flush lfsr 09 initlfsr2_f 4 wr 0c 0a initterm1_f 8 wr 00 termination sequence after flush operation 0b initterm2_f 8 wr 80 0c initterm3_f 4 wr 0b 10 vitberctrl_f 4 wr 0f viterbi ber measurement control flags 20 terrber1_f 8 r -- terrestrial channel error rate 21 terrber2_f 4 r -- 24 sat1ber1_f 8 r -- sat1 channel error rate 25 sat1ber2_f 4 r -- 28 sat2ber1_f 8 r -- sat2 channel error rate 29 sat2ber1_f 4 r -- 30 forcecorr_f 8 wr 1d forced correction value for prc preamble (1d hex) 31 rs_ctrl_f 4 wr 03 rs/rs input control configuration bits 32 rs_cnt_f 1 wrt 01 rs decoder error counter control 35 rs_byecnt1_f 8 r -- rs byte error counter 36 rs_byecnt2_f 6 r -- 37 rs_framecnt1_f 8 r -- rs frame error counter 38 rs_framecnt2_f 2 r -- 40 initseq_f 8 wr 1d initialization sequence for vd (prc preamble 1d hex) 42 rs1_terrbyteerr_f 5 r -- terr. reed-solomon block 1 error reporting 43 rs2_terrbyteerr_f 5 r -- terr. reed-solomon block 2 error reporting 44 rs1_satbyteerr_f 5 r -- sat. reed-solomon block 1 error reporting 45 rs2_satbyteerr_f 5 r -- sat. reed-solomon block 2 error reporting 46 rs_block_decis_f 2 r -- status of last reed-solomon diversity decision 50 irqmask_f 5 int 00 fec interrupt mask 51 irqstatus_f 5 int 00 fec interrupt status
STA400A 38/117 table 8. if sampling and control interface base address: 04 - address range: 00 - 20 relative address (hex) register name wl type reset value (hex) comment 00 agc_ctrl1 8 wr 88 terr. and sat. agc control register1 01 sagcref0 8 wr 90 satellite agc reference (lsb) 02 sagcref1 5 wr 01 satellite agc reference (msb) 03 sagcintg 8 wr 00 8msb of satellite agc integrator 04 tagcref0 8 wr 90 terrestrial agc reference (lsb) 05 tagcref1 5 wr 01 terrestrial agc reference (msb) 06 tagcintg 8 wr 00 8msb of terr. agc integrator 07 if_ctrl 2 wr 00 if sampling control register 08 8 wr 00 reserved 09 8 wr 00 reserved 0a seltstout 4 wr 00 block functional test output sel. 0b tstmuxctl 4 wr 00 cdec functional test output sel. 0c clkdiv_conf 2 wr 03 master clock programmable divider 0d qpsk_ber_ctrl wr 00 control of the interface for external ber measurement 0e reserved for future use 0f reserved for future use 10 control 8 wr 00 general purpose control 11 8 wr 00 reserved 12 8 r -- reserved 13 8 r -- reserved 14 8 r -- reserved 15 8 r -- reserved 17 irq1_mask 8 wr 00 interrupt #1 mask 19 irq1_status 8 pr 00 interrupt #1 status 1b 8 wr 00 reserved for future use 1d 8 pr 00 reserved for future use 1f status1 8 r -- general purpose status 20 8 r -- reserved for future use
39/117 STA400A table 9. pc bitsctream interface base address: 05 - address range: 00 - 06 relative address (hex) register name wl type reset value (hex) comment 00 pcdc_conf_0 7 wr 00 clock configuration for pc interface #0 01 pcdc_conf_1 7 wr 00 clock configuration for pc interface #1 02 pcsd_conf_0 6 wr 00 output data configuration for pc interface #0 03 pcsd_conf_1 6 wr 00 output data configuration for pc interface #1 04 pcsync_conf 8 wr 77 synchronization signals configuration for both interfaces 05 8 wr 00 reserved for future use 06 pc_alarm 2 pr 00 alarm signals for interface #0 and #1 table 10. tdm (section 2) base address: 06 - address range: 10 - f6 relative address (hex) register name wl type reset value (hex) comment 10 deltarefcyc1_m 8 r -- delta reference cycles for mcm frame sync 11 deltarefcyc2_m 5 r -- 20 mfpsyncmax_s1 8 wr 46 set the rightmost distance of sat1 mfp sync 21 mfpsyncmin_s1 8 wr 2f set the leftmost distance of sat1 mfp sync 22 mfpsyncmax_s2 8 wr 46 set the rightmost distance of sat2 mfp sync 23 mfpsyncmin_s2 8 wr 2f set the leftmost distance of sat2 mfp sync 24 mfpsyncmax_t 8 wr 11 set the rightmost distance of terrestrial mfp sync 25 mfpsyncmin_t 8 wr 29 set the leftmost distance of terrestrial mfp sync 30 xmem_type 1 wr 00 external memory device type 31 xmemrefcyc1 8 wr 75 external memory refresh cycle period 32 xmemrefcyc2 1 wr 01 34 xmemmode 2 wr 00 external memory management mode 35 xmemstatus 2 r -- external memory management status 36 xmemsterradr1 8 r -- external memory management self-test error address 37 xmemsterradr2 8 r -- 38 xmemsterradr3 8 r -- 40 udcycdelta1_t 8 wr 00 mfp cycle number up down delta 41 udcycdelta2_t 3 wr 00 42 cnt_prio 8 wr 80 mfp cycles time internal setting 43 ud_cycles1 8 wr 9c mfp cycle number adiustment. 44 ud_cycles2 3 wr 00
STA400A 40/117 relative address (hex) register name wl type reset value (hex) comment 45 framelen1 8 wr 00 tdm frame length 46 framelen2 8 wr ad 47 framelen3 8 wr 9d 48 deltacycles1 8 r -- mfp clock period monitor 49 deltacycles2 3 r -- 4a mfc1 8 r -- master frame counter 4b mfc2 3 r -- 4c mfc_lsb 7 r -- master frame counter (lsb) 4d tdm2enable 8 wr ff tdm management block enable 4e xmemfifolevel 4 r -- external memory write access buffer filling level 4f pciddatard1 8 r -- pcid table read register 50 pciddatard2 2 r -- 51 pciddatawr1 8 wrt 00 pcid number and pcid interface enable 52 pciddatawr2 2 wrt 00 53 pcidaddr 5 wr 00 address of the pcid in the table 54 prc_ti 8 wr c8 sets the time interval between the output of two prcs. 55 tscw_err 2 wr 00 sets what is done if the tscw has uncorrected errors 56 tscw_addrrd 8 wrt 00 start address of register of tscw table, which shall to be read 57 tscw_data 8 rt -- contents of addressed tscw word (enables autoincrement function of address when read access) 58 statuserr_t 2 r -- read management enable and error flag 59 mgmtctrl_t 4 wr 03 control vector for tdm management 5b tscw_addrcurr 8 r -- address of current register of tscw table, which is read 61-f0 bk1-bk144 8 trt ff tdm management bookkeeping matrix f5 irqmask_t 3 int 00 tdm interrupt mask f6 irqstatus_t 3 int 00 tdm interrupt status table 11. terrestrial demodulator (section 2) base address: 07 - address range: 10 - 81 relative address (hex) register name wl type reset value (hex) comment 10 cfcntgood1_m 8 pr 00 counter for coarse frequency good events 11 cfcntgood2_m 8 pr 00 table 10. tdm (section 2) (continued)
41/117 STA400A 15 cfcntbad1_m 8 pr 00 counter for coarse frequency bad events 16 cfcntbad2_m 8 pr 00 18 cfctrl_m 1 wr 00 control of cf algorithm 20 cf_minkexplow_m 8 wr 90 control of confidence threshold calculation for cf estimation 21 cf_diffkexpmaxlow_m 8 wr 08 control of confidence threshold calculation for cf estimation 22 cf_delta_kexplow_m 8 wr 01 control of confidence threshold calculation for cf estimation 23 cf_deltacntlow1_m 8 wr 20 control of confidence threshold calculation for cf estimation 24 cf_deltacntlow2_m 2 wr 00 26 cf_maxkexphigh_m 8 wr ff control of confidence threshold calculation for cf estimation 27 cf_diffkexpmaxhigh_m 8 wr 06 control of confidence threshold calculation for cf estimation 28 cf_deltakexphigh_m 8 wr 01 control of confidence threshold calculation for cf estimation 29 cf_deltacnthigh1_m 8 wr 01 control of confidence threshold calculation for cf estimation 2a cf_deltacnthigh2_m 2 wr 00 2b cf_initdelay_m 5 wr 17 control of initial behavior of cf estimation 2d cf_kexpthact_m 8 r -- current confidence threshold value 30 cf_estact1_m 8 r -- coarse frequency estimation of received amss before averaging 31 cf_estact2_m 8 r -- 35 cf_kestactexp_m 8 r -- coarse frequency confidence exponent of received amss before averaging 40 cf_est1_m 8 r -- coarse frequency estimation of received amss after averaging 41 cf_est2_m 8 r -- 45 cf_estexp_m 8 r -- coarse frequency confidence exponent of received amss after averaging 50 cf_avgest1_m 8 r -- current mcm cf averager estimate 51 cf_avgest2_m 8 r -- 55 cf_avgestexp_m 8 r -- current mcm cf averager confidence estimate 80 cf_avgctrl 8 wr b0 mcm coarse freq averager control vector 81 cf_avgminestconf_m 8 wr 00 mcm coarse freq averager: threshold for cf confidence table 11. terrestrial demodulator (section 2)
STA400A 42/117 2.2 qpsk demodulator (s1-early/s2-late) the two qpsk demodulators (s1-early and s2-late) have the same register set so they have been listed below once. the registers have different addresses and the same reset value except for the iffreq register. qpsk_demod_en - qpsk demodulator enable register this register disables the qpsk demodulator when bit-0 is set to '0'. when disabled the demodulator output is fixed to '0x00' or to '0x80' depending on the bit-4 setting of the qpsk_ctrl register (address 0x005a/0x0080) b7-b1: not used b0: dem_en 0=demodulator disabled; 1=demodulator enabled. qpsk_ctrl - qpsk demodulator control register this is a control register for the qpsk demodulator. b7: avg_off this bit disables the averager filter of the integrators. 0=averager filter enabled; 1=averager filter disabled. b6: nulofs_en this bit enables/disables the nulofs block. 0=disabled; 1=enabled. b5: reserved. b4: dem2tdm_fmt output data format. 0=two's complement; 1=offset binary. b3: iqswap this bit swaps the i and q component of the demodulator output. 0=no change; 1=swaps i with q. b2: qchs this bit inverts the q component sign in the i/q mixer. 0=no invertion; 1=sign invertion. b1: timchs this bit inverts the timing loop sign. 0=no invertion; 1=sign invertion. b0: carchs this bit inverts the carrier loop sign. 0=no invertion; 1=sign invertion. type: singlebyte - r/w word length: 1 byte name address (hex) bit map reset value (hex) qpsk_demod_en1 s1/s2 0059/007f 7-0 01 type: singlebyte - r/w word length: 8 byte name address (hex) bit map reset value (hex) qpsk_ctrl s1/s2 005a/0080 7-0 4f
43/117 STA400A pfdthr - phase/frequency error detector threshold this register sets the threshold for the frequency detector. the number format is positive integer. symfreq - symbol frequency this register sets the symbol frequency of the timing nco (equal to 1.64mhz for both satellite demodulators). it is 25 bit long and is divided into four bytes; symfreq0 is the lsb byte, symfreq3 is the msb. symfreq must be loaded with an interger value given by where f mclk = 23.92mhz is the master clock frequency, f sym is the symbol frequency and int(.) is the integer part of the number. iffreq - intemediate frequency this register sets the 2 nd intermediate carrier frequency of the i/q mixer. it is 28 bit long and is divided into four bytes; iffreq0 is the lsb byte, iffreq3 is the msb. iffreq must be loaded with an interger value given by where f mclk = 23.92mhz is the master clock frequency, f c is the second intermediate frequency (5.175mhz for s2-late satellite and 7.015mhz for s1-early satellite) and int(.) is the in- teger part of the number. type: singlebyte - r/w word length: 6 byte name address (hex) bit map reset value (hex) pfdthr s1/s2 005b/0081 5-0 14 type: multibytes - r/w word length: 25 byte name address (hex) bit map reset value (hex) symfreq3 s1/s2 005f/0085 24 00 symfreq2 s1/s2 005e/0084 23-16 23 symfreq1 s1/s2 005d/0083 15-8 1a symfreq0 s1/s2 005c/0082 7-0 8b type: multibytes - r/w word length: 28 byte name address (hex) bit map reset value (hex) iffreq3 s1/s2 0063/0089 27-24 04/03 iffreq2 s1/s2 0062/0088 23-16 b1/76 iffreq1 s1/s2 0061/0087 15-8 3b/27 iffreq0 s1/s2 0060/0086 7-0 14/62 symfreq int 0.5 f sym f mclk ------------------ 2 25 + ?? ?? ?? = iffreq int 0.5 f c f mclk ------------------ 2 28 + ?? ?? ?? =
STA400A 44/117 alfacar - carrier loop filter alpha parameter this register sets the proportional gain of the carrier loop. it must be loaded with a positive integer number from 0x00 to 0xff (0 to 255 decimal). b7-b0 : alpha positive integer, range 0 to 255 decimal. betacar - carrier loop filter beta parameter this register sets the integral gain of the carrier loop. the representation of the number is mantissa-exponent (base 2): beta = beta_m x 2 (beta_e) b7-b5 : beta_e exponent of the number. positive integer, range 0 to 7 decimal. b4-b0 : beta_m mantissa of the number. positive integer, range 0 to 31 decimal. alfatim - timing loop filter alpha parameter this register sets the proportional gain of the timing loop. it must be loaded with a positive integer number from 0x00 to 0xff (0 to 255 decimal). b7-b0 : alpha positive integer, range 0 to 255 decimal. betatim - timing loop filter beta parameter this register sets the integral gain of the timing loop. the representation of the number is mantissa-exponent (base 2): beta = beta_m x 2 (beta_e) b7-b5 : beta_e exponent of the number. positive integer, range 0 to 7 decimal. b4-b0 : beta_m mantissa of the number. positive integer, range 0 to 31 decimal. type: singlebyte - r/w word length: 8 byte name address (hex) bit map reset value (hex) alfacar s1/s2 0064/008a 7-0 17 type: singlebyte - r/w word length: 8 byte name address (hex) bit map reset value (hex) betacar s1/s2 0065/008b 7-0 15 type: singlebyte - r/w word length: 8 byte name address (hex) bit map reset value (hex) alfatim s1/s2 0066/008c 7-0 07 type: singlebyte - r/w word length: 8 byte name address (hex) bit map reset value (hex) betatim s1/s2 0067/008d 7-0 0e
45/117 STA400A rampctrl - frequency sweep control register this register controls the operation of the frequency sweep block. b7 :rfu b6 : slope 0=positive; 1=negative b5 : swon 0=sweep disabled; 1=sweep enabled b4 : swstep 0=multiply by 1; 1=multiply by 2 b3-b0 : stepper 0000=divide by 1 0001=divide by 2 . 1111=divide by 16 agc2beta - agc2 loop gain this register sets the agc2 loop gain according to the following formula: b agc2 = 2 agc2beta b7-b3 :not used b2-b0 : agc2beta 000 -> gain=1 011 -> gain=8 110 -> gain=64 001 -> gain=2 100 -> gain=16 111 -> gain=0 010 -> gain=4 101 -> gain=32 agc2ref - agc2 reference this registers sets the reference level or the agc2 loop. the format is positive integer from 0 to 255 decimal. b7-b0 : agc2ref positive integer, range 0 to 255 decimal agc2intg - 8 msbs of agc2 loop integrator this register contains the 8 msbs of the agc2 loop integrator. the format is twos complement. type: singlebyte - r/w word length: 7 byte name address (hex) bit map reset value (hex) rampctrl s1/s2 0068/008e 6-0 20 type: singlebyte - r/w word length: 3 byte name address (hex) bit map reset value (hex) agc2beta s1/s2 0069/008f 2-0 03 type: singlebyte - r/w word length: 8 byte name address (hex) bit map reset value (hex) agc2ref s1/s2 006a/0090 7-0 5a type: singlebyte - r/w word length: 8 byte name address (hex) bit map reset value (hex) agc2intg s1/s2 006b/0091 7-0 00
STA400A 46/117 timintg - 8 msbs of timing loop integrator this register contains the 8 msbs of the timing loop integrator. the format is twos complement. carintg - 8 msbs of carrier loop integrator this register contains the 8 msbs of the carrier loop integrator. the format is twos complement. carfreq - locked carrier frequency this register is 28 bit long and is divided into four bytes; carfreq0 is the lsb byte, carfreq3 is the msb. it contains the carrier frequency on which the demodulator is locked. the format is twos complement. cn - carrier to noise esteem this register gives the carrier to noise ratio estimation in db. the number has a fixed point format. b7 - b3 : integer part b2 - b0 : fractional part example : cn = 10010111 = (100101.11)bin = (37.75)dec => c/n = 37.75db flag - demodulator status register this is a read only register containing specific status bit of the demodulator. b7 : lock 0=demodulator locked; 1=demodulator unlocked b6 : timintg_clr 0=timing integrator cleared; 1=timing integrator active type: singlebyte - r/w word length: 8 byte name address (hex) bit map reset value (hex) timintg s1/s2 006c/0092 7-0 00 type: singlebyte - r/w word length: 8 byte name address (hex) bit map reset value (hex) carintg s1/s2 006d/0093 7-0 00 type: multibytes - r word length: 28 byte name address (hex) bit map reset value (hex) carfreq3 s1/s2 0071/0097 27-24 -- carfreq2 s1/s2 0070/0096 23-16 -- carfreq1 s1/s2 006f/0095 15-8 -- carfreq0 s1/s2 006e/0094 7-0 -- type: singlebyte - r word length: 8 byte name address (hex) bit map reset value (hex) cn s1/s2 0072/0098 7-0 -- type: singlebyte - r word length: 4 byte name address (hex) bit map reset value (hex) flag s1/s2 0073/0099 7-4 --
47/117 STA400A b5 : carintg_clr 0=carrier integrator cleared; 1=carrier integrator active b4 : clr_ramp 0=ramp cleared; 1=ramp active b3 - b0 :rfu nulofs_win - null carrier offset window the carriernulloffset block writes the new if frequency in the carrier nco if the demodulator lock signal is low for a period of time equal to the value written in this register. the window length is given in msec. b3 - b0 : nulofs_win 0000 -> 10msec 0100 -> 50msec 1000 -> 175msec 1100 -> 350msec 0001 -> 20msec 0101 -> 100msec 1001 -> 200msec 1101 -> 400msec 0010 -> 30msec 0110 -> 125msec 1010 -> 250msec 1110 -> 450msec 0011 -> 40msec 0111 -> 150msec 1011 -> 300msec 1111 -> 500msec nulofs_deltaf - null carrier offset delta frequency the carriernulloffset block subtracts from the locked carrier frequency the value contains in this register before writing the new if frequency in the carrier nco. the register format is twos complent. given a frequency freq in hz, the value to load in the register is given by: where int(.) is the integer function. timlpf_ctrl - timing loop filter control this register controls the operation of the timing loop filter. b7 : timavg_off 0=self-noise filter enabled; 1=self-noise filter disabled. b6-b5 : timintg_clr_win 00 -> window=10sec 10 -> window=40sec 01 -> window=20sec 11 -> window=60sec b4 : timintg_clr_en 0=timintgctrl block disabled; 1=timintgctrl block enabled type: singlebyte - r/w word length: 4 byte name address (hex) bit map reset value (hex) nulofs_win s1/s2 0074/009a 3-0 07 type: singlebyte - r/w word length: 8 byte name address (hex) bit map reset value (hex) nulofs_deltaf s1/s2 0075/009b 7-0 2b type: singlebyte - r/w word length: 8 byte name address (hex) bit map reset value (hex) timlpf_ctrl s1/s2 0076/009c 7-0 90 nulofs_deltaf int freq 2 28 512f mclk ---------------------------- - 0.5 + =
STA400A 48/117 b3 :rfu b2-b0 : timlpf_length 000 -> timing integrator bit length =8 100 -> timing integrator bit length =14 001 -> timing integrator bit length =9 101 -> timing integrator bit length =16 010 -> timing integrator bit length =10 110 -> timing integrator bit length =18 011 -> timing integrator bit length =12 111 -> timing integrator bit length =20 lockthr - lock detector threshold this register sets the threshold for the lock detector block. b1-b0 : lockthr 00 -> threshold = 32 dec 01 -> threshold = 64 dec 10 -> threshold = 80 dec 11 -> threshold = 96 dec 2.3 terrestrial demodulator (section 1) enable_m - mcm demodulator enable register mcm submodules enable signals. enable active on 1. b7 : mrm_ff_demod_en enable of fine frequency submodule b6 : mrm_fc_demod_en enable of frequency control submodule b5 : mrm_cf_demod_en enable of coarse frequency submodule b4 : mrm_ss_demod_en enable of symbol synchronization submodule b3 : mrm_fs_demod_en enable of frame synchronization submodule b2 : mrm_pp_demod_en enable of pre processing submodule b1 : mrm_fft_demod_en enable of fft submodule b0 : mrm_iqg_demod_en enable of i/q generation submodule status_m - mcm demodulator status register status information of mcm submodule type: singlebyte - r/w word length: 2 byte name address (hex) bit map reset value (hex) lockthr s1/s2 0077 1-0 02 type: singlebyte - r/w word length: 8 byte name address (hex) bit map reset value (hex) enable_m 0100 7-0 ff type: multibytes - r word length: 10 byte name address (hex) bit map reset value (hex) status2_m 0102 9-8 -- status1_m 0101 7-0 --
49/117 STA400A b9 : mfc_freq_lock 0= no lock; 1= lock b8 : mff_ff_state 0=idle; 1= operational b7-b6 : mfc_fc_state 00= idle 01= init 10= tracking 11= freeze b5 : mcf_cf_state 0=idle; 1= operational b4 : mss_ss_state 0= idle; 1= active (channel window active) b3-b2 : mfs_fs_state 00= idle 01= hunt 10= pre sync 11= sync b1 : mpp_pp_state 0=idle; 1= operational b0 : mfft_fft_state 0=idle; 1= operational dataovf_m - mcm demodulator blocks overflow register overflow bit event counter of iqgen, lpf and nco.the internal overflow bits are ored and counted. this may be an indication that the input signal is to strong so that internal overflow occurs. iqgmode_m - iq generation mode inverts and interchanges of i and q at the output of the iq generation. required for a,b ensemble switch. for ensemble a value of 02h and for ensemble b the default value of 00h must be used. b2 : interchange of re and im data b1 : sign invertion of im data b0 : sign invertion of re data clk_devcomp_m - clock deviation compensation mode b0 : 1=signal coming from tdm management will be used 0=signal coming from register map (cyclecntre) will be used type: singlebyte - pr word length: 8 byte name address (hex) bit map reset value (hex) dataovf_m 0104 7-0 00 type: singlebyte - r/w word length: 3 byte name address (hex) bit map reset value (hex) iqgmode_m 0106 2-0 02 type: singlebyte - r/w word length: 1 byte name address (hex) bit map reset value (hex) clk_devcomp_m 0107 0 01
STA400A 50/117 amssthrl_m - amss detection low threshold if the correlation exceeds this threshold a valid amss sequence is recognized and the channel window is start- ed. amssthrh_m - amss detection high threshold this threshold is used in addition to mrm_amss_low_corr_th to improve performance for good channels show- ing a high correlation value. amssfailed_m - amss not detected event this register sets the number of events that are necessary to reach the sync state within syncsearch_m sub- sequent frame_windows . otherwise the state machine will be set back to the hunt state. syncsearch_m - pre-synch mcm frames number see amssfailed_m for description syncloss_m - number of allowed amss failed event if amss failed events equal to the value ste in this register occurs subsequently, the state machine will be set back to the hunt state. type: singlebyte - r/w word length: 7 byte name address (hex) bit map reset value (hex) amssthrl_m 0108 6-0 37 type: singlebyte - r/w word length: 7 byte name address (hex) bit map reset value (hex) amssthrh_m 0109 6-0 41 type: singlebyte - r/w word length: 3 byte name address (hex) bit map reset value (hex) amssfailed_m 010a 2-0 07 type: singlebyte - r/w word length: 4 byte name address (hex) bit map reset value (hex) syncsearch_m 010b 3-0 0a type: multibytes - r/w word length: 11 byte name address (hex) bit map reset value (hex) syncloss2_m 010d 10-8 03 syncloss1_m 010c 7-0 ff
51/117 STA400A framelen_m - amss detection frame window length this register sets the window value within which, before and after the expected amss sequence, the occurance of the amss sequence is searched. value corresponds to mcm symbol rate channellen_m - amss detection channel window length window while searching for higher amss correlation peaks. value corresponds to mcm symbol rate. cyclecnt_m - mcm frame cycle count difference wrt nominal value this value is computed due to the internal clock adjustment based on mfp evaluation. cyclecntref_m - mcm frame cycle count difference setting external setting of actual difference of mcm-frame cycle count to nominal value. attfactor_m - attenuation factor attenuation factor for correlation results inside channel window. used for determination of guard window posi- tion. type: singlebyte - r/w word length: 8 byte name address (hex) bit map reset value (hex) framelen_m 010e 7-0 b4 type: singlebyte - r/w word length: 8 byte name address (hex) bit map reset value (hex) channellen_m 010f 7-0 b4 type: multibytes - r word length: 12 byte name address (hex) bit map reset value (hex) cyclecnt2_m 0111 11-8 -- cyclecnt1_m 0110 7-0 -- type: multibytes - wrt word length: 12 byte name address (hex) bit map reset value (hex) cyclecntref2_m 0113 11-8 00 cyclecntref1_m 0112 7-0 00 type: multibytes - r/w word length: 13 byte name address (hex) bit map reset value (hex) attfactor2_m 0116 12-8 1f attfactor1_m 0115 7-0 f0
STA400A 52/117 attenuation function: ; a (k + 1) = a (k) +b k 0 = channel window length (in symbol rate) , a = attenuation factor (in db) and b= corr_weight_factor / 2 13 constant channel window (ko=180 samples): constant attenuation (3db): histlen_m - history register length stores the last 15 shift operations of the window start position. the chosen value will restrict the array out of which the minimum shift operation will be searched. b3-b0 : 0000=current correlation maximum will be proceeded . 1111=current and the last 15 correlation positions will be taken account cn_m - estimated noise ans signal to noise power uses 12 adjacent carriers besides the active carriers. estimates power within these 24 adjacent carriers (mff_n_guard) and power within all 637 active carriers (mff_cpn_act). b23-b12 : mff_n_guard b11-b0 : mff_cpn_act attenuation b (*2 13 ) 0db 8192 3db 8184 6db 8176 12db 8160 channel window b(*2 13 ) 180 8184 90 8176 45 8160 type: singlebyte - r/w word length: 4 byte name address (hex) bit map reset value (hex) histlen_m 0117 3-0 0f type: multibytes - r word length: 24 byte name address (hex) bit map reset value (hex) cn3_m 011b 23-16 -- cn2_m 011a 15-8 -- cn1_m 0119 7-0 -- a k () 10 k 2k 0 --------- a 20db -------------- = b10 k 2k 0 --------- a 20db -------------- =
53/117 STA400A ffctrl_m - fine frequency control register if mrm_ff_fed_mean_en is set to 1 the ouput of the fed is averaged over two adjacent mcm symbols. if mrm_ff_lpf_sel is set to 1 an it1 controller is implemented, otherwise a pure i controller. the mrm_ff_alpha value determines the integral part for both it1 and i controller. b5-b2 : mrm_ff_alpha b1 : mrm_ff_lpf_set b0 : mrm_ff_fed_mean_en ffbeta_m - fine frequency loop filter beta constant if mrm_ff_lpf_sel is set to 1 the mrm_ff_beta value sets the proportional part for the it1 controller. for a pure i controller mrm_ff_beta is not used. blkdetect_m - frequency control blockage condition during blockage (mrm_blockage_detect = 1) the frequency control state is set to freeze. in that state the frequency offset is held and no further actions are untertaken. b0 : mrm_blockage_detect initdelay_m - fine frequency statup delay this register sets the number for which the frequency control remains within the init state before entering the tracking state, i.e. the corresponding number of fine frequency estimates are discarded after external reset or internal clear. type: singlebyte - r/w word length: 6 byte name address (hex) bit map reset value (hex) ffctrl_m 011c 5-0 1e type: singlebyte - r/w word length: 8 byte name address (hex) bit map reset value (hex) ffbeta_m 011d 7-0 04 type: singlebyte - r/w word length: 1 byte name address (hex) bit map reset value (hex) blkdetect_m 011f 0 00 type: singlebyte - r/w word length: 2 byte name address (hex) bit map reset value (hex) initdelay_m 0120 1-0 00
STA400A 54/117 maxfreq_m - fine frequency out-of-range setting maximum allowed difference of fine frequency and coarse frequency estimation to detect out-of-range con- dition of ff. if the difference between fine and coarse frequency estimation is equal or larger than this value, the fine frequency is considered out of range and is internally cleared. the value is in units of 91.25hz (2.99e6/ 32368). mincf_m - coarse frequency estimation confidence value only coarse frequency estimations with a confidence value equal or larger than the value set in this register are considered as valid and loaded into the internal coarse frequency estimation value register. cfref_m - coarse frequency offset setting external value for coarse frequency estimation. this value will be overwritten if the coarse frequency delivers valid estimations. the value is in units of 91.25hz (2.99e6/32768). cfvalue_m - coarse frequency offset value the value is in units of 91.25hz (2.99e6/32768). type: multibytes - r/w word length: 13 byte name address (hex) bit map reset value (hex) maxfreq2_m 0122 12-8 00 maxfreq1_m 0121 7-0 46 type: singlebyte - r/w word length: 8 byte name address (hex) bit map reset value (hex) mincf_m 0123 7-0 90 type: multibytes - wrt word length: 13 byte name address (hex) bit map reset value (hex) cfref2_m 0125 12-8 00 cfref1_m 0124 7-0 00 type: multibytes - r word length: 13 byte name address (hex) bit map reset value (hex) cfvalue2_m 0127 12-8 -- cfvalue1_m 0126 7-0 --
55/117 STA400A ffscale_m - fine frequency scale factor factor that is multiplied with the fine frequency estimates to get the frequency controls internally used esti- mate. the msb bit has a weight of 0.5, i.e. a value of ff h is interpreted as a factor of 255/256. this value has to considered together with the control constants of the fine frequency control loop. ff_oor_m - fine frequency out-of-range counter this counter counts up if the fine frequency estimate is considered as out of range and the fine frequency control loop is reset (see register max freq_m, addr: 0x0121/22). epocen_m - error phase offset correction enable if this bit is set, the epoc algorithm inside the post processing is enabled demapctrl_m - demapping control the re and im input values are cross added to get the output re and im values corresponding to the metric used for the fec. this register determines this metric generation calculations. b7 : sign control inverts re input value for the re output b6 : sign control inverts im input value for the re output b5 : sign control inverts re input value for the im output b4 : sign control inverts im input value for the im output b3 : pass control force zero of re input value for the re output b2 : pass control force zero of im input value for the re output b1 : pass control force zero of re input value for the im output b0 : pass control force zero of im input value for the im output type: singlebyte - r/w word length: 8 byte name address (hex) bit map reset value (hex) ffscale_m 0128 7-0 e0 type: singlebyte - pr word length: 8 byte name address (hex) bit map reset value (hex) ff_oor_m 012a 7-0 00 type: singlebyte - r/w word length: 1 byte name address (hex) bit map reset value (hex) epocen_m 0133 0 01 type: singlebyte - r/w word length: 8 byte name address (hex) bit map reset value (hex) demapctrl_m 0134 7-0 e0
STA400A 56/117 epocthr_m - error phase offset correction threshold only carriers with a re value equal or larger than mrm_epoc_thresh are taken for the epoc internally calcula- tions. the value is relative to the dynamic range of the signal. a value of 0fff corresponds to 2047/2048. the msb must be set always to 0. normshift_m - fft normalization normalization factor for fft output. this register scales the fft output by a factor of 2 norm_shift_m . (mantissa only) linscale_m - fft output linear scaling the register mrm_lin_scale performs a linear scaling of the fft output data. the register values from 0 to 255 correspond to an actual scaling factor of lin_scale_m/128, i.e. from 0 to 255/128. the default of 128 corre- sponds to a scaling factor of 1.0. shiftovfl_m - normshift overflow counter overflow counter of fft shift and norm shift together. the counter trigger is set if the normalization 0x37 is too large so that overall scaling is too large. limitovfl_m - pre processing overflow counter overflow event counter if the range of scale fft data exceeds input range of preprocessing. type: multibytes - r/w word length: 14 byte name address (hex) bit map reset value (hex) epocthr2_m 0136 13-8 06 epocthr1_m 0135 7-0 00 type: singlebyte - r/w word length: 4 byte name address (hex) bit map reset value (hex) normshift_m 0137 3-0 0b type: singlebyte - r/w word length: 8 byte name address (hex) bit map reset value (hex) linscale_m 0138 7-0 80 type: singlebyte - pr word length: 8 byte name address (hex) bit map reset value (hex) shiftovfl_m 0139 7-0 00 type: singlebyte - pr word length: 8 byte name address (hex) bit map reset value (hex) limitovfl_m 013b 7-0 00
57/117 STA400A epoccarriers_m - number of carrier for error phase offset correction shows the number of utilized active sub-carriers to compute epoc correction phasor for current mcm symbol. number can range from 0 to 636 (=0x27c). epocrotre_m - error phase offset correction phasor (real part) real part of epoc correction phasor. the value is in 2s complement with a range from -1 to 1 C 2 -7 quantized with 8 bits . epocrotim_m - error phase offset correction phasor (imaginary part) imaginary part of epoc correction phasor. the value is in 2s complement with a range from -1 to 1 C 2 -7 quan- tized with 8 bits. psframecnt_m - frame counter in pre sync state counter of frames during presync state ps_noamsscnt_m - frame counter without amss detection amssfailcnt_m - sequent frame counter without amss detection counter of sequent frames without amss detection during sync state. it will be reset after one succesfull detec- tion type: multibytes - r word length: 10 byte name address (hex) bit map reset value (hex) epoccarriers2_m 013d 9-8 -- epoccarriers1_m 013c 7-0 -- type: singlebyte - r word length: 8 byte name address (hex) bit map reset value (hex) epocrotre_m 013e 7-0 -- type: singlebyte - r word length: 8 byte name address (hex) bit map reset value (hex) epocrotim_m 013f 7-0 -- type: singlebyte - r word length: 4 byte name address (hex) bit map reset value (hex) psframecnt_m 0140 3-0 -- type: singlebyte - r word length: 3 byte name address (hex) bit map reset value (hex) ps_noamsscnt_m 0141 2-0 -- type: multibytes - r word length: 16 byte name address (hex) bit map reset value (hex) amssfailcnt2_m 0143 15-8 -- amssfailcnt1_m 0142 7-0 --
STA400A 58/117 oivlamssfail_m - amss failed detection number number of failed amss detections during an interval whose length can be set by register adr. 0x0196/96 maxcorriw_m - maximum correlation inside channel window maxcorrow_m - maximum correlation outside channel window mincorriw_m - minimum correlation inside channel window mincorrow_m - minimum correlation outside channel window frametoggle_m - frame toggle flag register type: multibytes - r word length: 12 byte name address (hex) bit map reset value (hex) oivlamssfail2_m 0145 11-8 -- oivlamssfail1_m 0144 7-0 -- type: singlebyte - rt word length: 7 byte name address (hex) bit map reset value (hex) maxcorriw_m 0147 6-0 -- type: singlebyte - rt word length: 7 byte name address (hex) bit map reset value (hex) maxcorrow_m 0149 6-0 -- type: singlebyte - rt word length: 7 byte name address (hex) bit map reset value (hex) mincorriw_m 014b 6-0 -- type: singlebyte - rt word length: 7 byte name address (hex) bit map reset value (hex) mincorrow_m 014d 6-0 -- type: singlebyte - r word length: 1 byte name address (hex) bit map reset value (hex) frametoggle_m 014f 0 --
59/117 STA400A corrmaxakt_m - actual maximum correlation inside channel window this value stores the actual weighted maximum correlation value inside the channel window corrmaxpos_m - actual correlation position inside frame window this value stores the actual position inside the channel window of weighted maximum correlation value: posshift_m - shift after history checking winjump_m - window jump ncoinc_m - nco increment the register provides the current nco increment. the value is in 2s complement with a resolution of 5.703 hz per lsb. this corresponds to a maximum control range of 2 16 * 5.703 hz= 373.75 khz ( 156 ppm @ 2.4 ghz). type: singlebyte - r word length: 7 byte name address (hex) bit map reset value (hex) corrmaxakt_m 0150 6-0 -- type: multibytes - r word length: 11 byte name address (hex) bit map reset value (hex) corrmaxpos2_m 0152 10-8 -- corrmaxpos1_m 0151 7-0 -- type: multibytes - r word length: 12 byte name address (hex) bit map reset value (hex) posshift2_m 0154 11-8 -- posshift1_m 0153 7-0 -- type: multibytes - r word length: 11 byte name address (hex) bit map reset value (hex) winjump2_m 0156 10-8 -- winjump1_m 0155 7-0 -- type: multibytes - r word length: 17 byte name address (hex) bit map reset value (hex) ncoinc3_m 0162 16 -- ncoinc2_m 0161 15-8 -- ncoinc1_m 0160 7-0 --
STA400A 60/117 ffest_m - actual fine frequency value the register provides the current value of the fine frequency contribution to the nco increment. the value is in 2s complement with a resolution of 5.703 hz per lsb. mctlen_m - mcm demodulator control mcm control is enabled if his register is set to 1, disabled if set to 0. the reset value enables this block. mctlmask_m - mcm demodulator control mask this register is a mask vector for internal state transitions and output control signals of mcm control. the output signals are masked out, i.e. set to logic 0, when the corresponding output mask bit (bits 0,1 or 2) is set to 0. by default the outputs are not masked. if transition mask 2 (bit 5) is set to 0, signal full_avg_len of the mcm cf averager is taken as is, otherwise it is internally forced to 1. if transition mask 1 (bit 4) is set to 0, the transition from state no_update to tdm_lock of mcm control is disabled. by default it is enabled. if transition mask 0 (bit 3) is set to 0, the transition from state no_update to fs_lock of mcm control is disabled. by default it is enabled. setting bits 3 and 4 to 0 means that after entering the state no_update this state is not left except when forced by a block disable (reg. 0x180 set to 0) or an external initialization (reg 0x182 set to 1). b5 : full_avg_len b4 : tdm_lock b3 : fs_lock b2 : timeout_disa b1 : fc_noup b0 : fs_init type: multibytes - r word length: 17 byte name address (hex) bit map reset value (hex) ffest3_m 0172 16 -- ffest2_m 0171 15-8 -- ffest1_m 0170 7-0 -- type: singlebyte - r/w word length: 1 byte name address (hex) bit map reset value (hex) mctlen_m 0180 0 00 type: singlebyte - r/w word length: 6 byte name address (hex) bit map reset value (hex) mctlmask_m 0181 5-0 1f
61/117 STA400A mctlinit_m - mcm demodulator control initialization trigger setting this register to 1 will trigger an intialization of mcm control when not already in state idle (then no action would occur). this action also triggers an initialization of mcm frame sync and mcm coarse frequency. tdmcntth_m - number of tdm frames in lock the register value corresponds to the number of subsequent tdm frames which have to be in lock before state no_update is entered. mctlstate_m - mcm demodulator control status this register displays the internal state of mcm control. b1-b0 : 00 -> status=idle 01 -> status=fs_lock 10 -> status=tdm_lock 11 -> status=no_update meanabs_m - mcm demodulator output symbols mean the register provides the mean of the amplitude of real and imaginary part of the mcm output symbols. the value range is from 0 to 255 =0xff. the absolute value is in multiples of 1/256. cliprate_m - mcm demodulator output clip rate the register provides the clipping rate of the mcm output. the value range is from 0 to 0xff (255). the clipping rate is in multiples of 1/256, i.e. 0xff corresponds to full clipping, 0x80 to 50% clipping rate. type: singlebyte - r/w word length: 1 byte name address (hex) bit map reset value (hex) mctlinit_m 0182 0 00 type: singlebyte - r/w word length: 8 byte name address (hex) bit map reset value (hex) tdmcntth_m 0183 7-0 18 type: singlebyte - r word length: 2 byte name address (hex) bit map reset value (hex) mctlstate_m 0184 1-0 -- type: singlebyte - r word length: 8 byte name address (hex) bit map reset value (hex) meanabs_m 0190 7-0 -- type: singlebyte - r word length: 8 byte name address (hex) bit map reset value (hex) cliprate_m 0191 7-0 --
STA400A 62/117 oivllenamssfail_m - observation interval length this register sets the length of observation interval of the register oivlamssfail (addr: 0x0144/45). ; mcm frame length: t mf =7,2 msec b11-b0 : 0x086 -> interval (t ivl ) = 1.0 sec 0x2b6 -> interval (t ivl ) = 5.0 sec 0x56c -> interval (t ivl ) = 10.0 sec 0x823 -> interval (t ivl ) = 15.0 sec 0xad9 -> interval (t ivl ) = 20.0 sec 0xfff -> interval (t ivl ) = 29.5 sec winjplimit_m - maximum allowed window jump jp_limit = t jp /t s ; sample frequency f s =5.98 mhz ; t s =0.167 sec b10-b0 : 0x003 -> jump (t jp ) = 0.5 usec 0x01e -> jump (t jp ) = 5.0 usec 0x03c -> jump (t jp ) = 10.0 usec 0x05a -> jump (t jp ) = 15.0 usec 0x078 -> jump (t jp ) = 20.0 usec 0x168 -> jump (t jp ) = 60.0 usec jplimitevt_m - jump limit events counter type: multibytes - r/w word length: 12 byte name address (hex) bit map reset value (hex) oivllenamssfail2_m 0196 11-8 0f oivllenamssfail1_m 0195 7-0 8b type: multibytes - r/w word length: 11 byte name address (hex) bit map reset value (hex) winjplimit2_m 0198 10-8 00 winjplimit1_m 0197 7-0 03 type: singlebyte - pr word length: 8 byte name address (hex) bit map reset value (hex) jplimitevt_m 019a 7-0 00 oivllen t ivl t mf ---------- - =
63/117 STA400A winjpnolimit_m - actual requested window jump w/o limit actual requesteted jump of window without limit function. (see table of register adr 0x097/98). iqgdataovf_m - iqgen lpf overflow counter event counter of overflow bit of halfband filter in iq generator ncodataovf_m - nco overflow counter event counter of overflow bit of nco lpfdataovf_m - lpf overflow counter event counter of ored overflow bits of halfband filters in the low pass filterf irqmask_m - mcm demodulator interrupt mask if the mask bits are set the corresponding interrupt is enabled, i.e. if the irq_status_m bit is set an external in- terupt is generated. b1 : frequency unlock b0 : frame sync unlock type: multibytes - r/w word length: 11 byte name address (hex) bit map reset value (hex) winjpnolimit2_m 019c 10-8 00 winjpnolimit1_m 019b 7-0 00 type: singlebyte - pr word length: 8 byte name address (hex) bit map reset value (hex) iqgdataovf_m 01b0 7-0 00 type: singlebyte - pr word length: 8 byte name address (hex) bit map reset value (hex) ncodataovf_m 01b2 7-0 00 type: singlebyte - pr word length: 8 byte name address (hex) bit map reset value (hex) lpfdataovf_m 01b4 7-0 00 type: singlebyte - int word length: 2 byte name address (hex) bit map reset value (hex) irqmask_m 01c0 1-0 00
STA400A 64/117 irqstatus_m - mcm demodulator interrupt status bit 0 is set if the frequency control is enabled (cf. bit 6 of enable_m) and the frequency lock indicator has changed from lock to no lock (cf. bit 9 of status_m). this bit is set if the frame sync is enabled (cf. bit 3 of enable_m) and the its state has changed from sync to hunt (cf. bit 3-2 of status_m). b1 : frequency unlock b0 : frame sync unlock 2.4 tdm (section 1) tdmenable_s - satellite tdm decoding block enable b7 : sat2_tfm_en enable sub-block satellite two tdm fifo management b6 : sat2_td_en enable sub-block satellite two tdm de-scrambling b5 : sat2_qmg_en enable sub-block satellite two qpsk metric generation b4 : sat2_ts_en enable sub-block satellite two tdm synchronization b3 : sat1_tfm_en enable sub-block satellite one tdm fifo management b2 : sat1_td_en enable sub-block satellite one tdm de-scrambling b1 : sat1_qmg_en enable sub-block satellite one qpsk metric generation b0 : sat1_ts_en enable sub-block satellite one tdm synchronization tdmsync_s1 - satellite one tdm decoding synchronization data control t b4 : fsm_fallback b3 : invert_data_out b2 : invert_data_in b1 : iq_swap_data_out b0 : iq_swap_data_in type: singlebyte - int word length: 2 byte name address (hex) bit map reset value (hex) irqstatus_m 01c1 1-0 00 type: singlebyte - r/w word length: 8 byte name address (hex) bit map reset value (hex) tdmenable_s 0200 7-0 ff type: singlebyte - r/w word length: 5 byte name address (hex) bit map reset value (hex) tdmsync_s1 0204 4-0 10
65/117 STA400A mfplength_s1 - sat1 tdm decoding extended mfp detection window length once the mfp is found the subsequent appearance is scanned within this symmetric window around the mfp's predicted position on the soft-symbol stream. mfpthr_s1 - sat1 tdm decoding extended mfp detection threshold threshold of the extended mfp correlation determining extended mfp detection if reached or exceeded. synclength_s1 - sat1 tdm decoding synchronization window length number of (predicted) subsequent extended mfp positions which are evaluated to determine the status of the mfp synchronization. presyncthr_s1 - sat1 tdm decoding pre-synchronization lost threshold number of undetected extended mfp's within the tdm decoding synchronization window, forcing the tdm syn- chronization to reenter the initial synchronization procedure searching the extended mfp on the entire soft-sym- bol stream. . value 0x00 disables loss of lock. syncthr_s1 - sat1 tdm decoding synchronization lost threshold number of subsequent undetected extended mfp's while being sychronized, forcing the tdm synchronization to reenter the initial synchronization procedure searching the extended mfp on the entire soft-symbol stream. (long range drop-out condition). type: singlebyte - r/w word length: 4 byte name address (hex) bit map reset value (hex) mfplength_s1 0205 3-0 0f type: singlebyte - r/w word length: 7 byte name address (hex) bit map reset value (hex) mfpthr_s1 0206 6-0 44 type: singlebyte - r/w word length: 4 byte name address (hex) bit map reset value (hex) synclength_s1 0207 3-0 03 type: singlebyte - r/w word length: 4 byte name address (hex) bit map reset value (hex) presyncthr_s1 0208 3-0 02 type: singlebyte - r/w word length: 4 byte name address (hex) bit map reset value (hex) syncthr_s1 0209 3-0 0b
STA400A 66/117 fspthr_s1 - sat1 tdm decoding fsp invalid threshold threshold of the fsp correlation determining an invalid fsp detection if not exceeded. metricctrl_s1 - satellite one tdm decoding qpsk metric generation data control enables swap of data i- and q-component and qpsk-map inversion if the corresponding bit is set. determines the threshold of the soft decision slicer and the applied data output format. b3 : mgen_map_inv b2 : mgen_format 0 = two's complement; 1= offset binary b1 : mgen_lim_thold 0-> threshold = (64)dec; 1-> threshold = (80)dec b0 : mgen_iq_swap_data_in scrambler_s1 - satellite one tdm decoding scrambler polinomial tdmsync_s2 - satellite two tdm decoding synchronization data control b4 : fsm_fallback b3 : invert_data_out b2 : invert_data_in b1 : iq_swap_data_out b0 : iq_swap_data_in type: singlebyte - r/w word length: 6 byte name address (hex) bit map reset value (hex) fspthr_s1 020a 5-0 14 type: singlebyte - r/w word length: 4 byte name address (hex) bit map reset value (hex) metricctrl_s1 020b 3-0 00 type: multibytes - r/w word length: 12 byte name address (hex) bit map reset value (hex) scrambler2_s1 020d 11-8 08 scrambler1_s1 020c 7-0 05 type: singlebyte - r/w word length: 5 byte name address (hex) bit map reset value (hex) tdmsync_s2 0212 4-0 10
67/117 STA400A mfplength_s2 - sat2 tdm decoding extended mfp detection window length once the mfp is found the subsequent appearance is scanned within this symmetric window around the mfp's predicted position on the soft-symbol stream. mfpthr_s2 - sat2 tdm decoding extended mfp detection threshold threshold of the extended mfp correlation determining extended mfp detection if reached or exceeded. synclength_s2 - sat2 tdm decoding synchronization window length number of (predicted) subsequent extended mfp positions which are evaluated to determine the status of the mfp synchronization. presyncthr_s2 - sat2 tdm decoding pre-synchronization lost threshold number of undetected extended mfp's within the tdm decoding synchronization window, forcing the tdm syn- chronization to reenter the initial synchronization procedure searching the extended mfp on the entire soft-sym- bol stream. . value 0x00 disables loss of lock. syncthr_s2 - sat2 tdm decoding synchronization lost threshold number of subsequent undetected extended mfp's while being sychronized, forcing the tdm synchronization to reenter the initial synchronization procedure searching the extended mfp on the entire soft-symbol stream. (long range drop-out condition). type: singlebyte - r/w word length: 4 byte name address (hex) bit map reset value (hex) mfplength_s2 0213 3-0 0f type: singlebyte - r/w word length: 7 byte name address (hex) bit map reset value (hex) mfpthr_s2 0214 6-0 44 type: singlebyte - r/w word length: 4 byte name address (hex) bit map reset value (hex) synclength_s2 0215 3-0 03 type: singlebyte - r/w word length: 4 byte name address (hex) bit map reset value (hex) presyncthr_s2 0216 3-0 02 type: singlebyte - r/w word length: 4 byte name address (hex) bit map reset value (hex) syncthr_s2 0217 3-0 0b
STA400A 68/117 fspthr_s2 - sat2 tdm decoding fsp invalid threshold threshold of the fsp correlation determining an invalid fsp detection if not exceeded. metricctrl_s2 - satellite one tdm decoding qpsk metric generation data control enables swap of data i- and q-component and qpsk-map inversion if the corresponding bit is set. determines the threshold of the soft decision slicer and the applied data output format. b3 : mgen_map_inv b2 : mgen_format 0 = two's complement; 1= offset binary b1 : mgen_lim_thold 0-> threshold = (64)dec; 1-> threshold = (80)dec b0 : mgen_iq_swap_data_in scrambler_s2 - satellite two tdm decoding scrambler polinomial mfplock_s1 - satellite one tdm decoding status b6-b5 : tdm_sync 00= idle 10= fsp resync 01= xmfp hunt 11= xmfp resync b4-b3 : tdm_dropout_align 00= idle 10= medium 01= short 11= long b2-b1 : tdm_sync_status 00= idle/flush 10= sync 01= presync 10= sync b0 : tdm_lock 0= unlock; 1= lock mfplost_s1 - satellite one tdm decoding extended mfp counter number of extended mfp's not found within the synchronization window whilest presynchronized (range from 0 to the value loaded into the register presyncthr_s1, addr:0x0208) or subsequent not found whilest synchro- nized (range from 0 to the value loaded into the register syncthr_s1, addr:0x0209). type: singlebyte - r/w word length: 6 byte name address (hex) bit map reset value (hex) fspthr_s2 0218 5-0 14 type: multibytes - r/w word length: 12 byte name address (hex) bit map reset value (hex) scrambler2_s2 021b 11-8 08 scrambler1_s2 021a 7-0 05 type: singlebyte - r word length: 7 byte name address (hex) bit map reset value (hex) mfplock_s1 021d 6-0 -- type: singlebyte - r word length: 4 byte name address (hex) bit map reset value (hex) mfplost_s1 021e 3-0 --
69/117 STA400A mfpw_re_s1 - satellite one tdm decoding extended mfp correlation weight, real part result of the latest extended mfp real part correlation. mfpw_im_s1 - satellite one tdm decoding extended mfp correlation weight, imaginary part result of the latest extended mfp imaginary part correlation. fspw_re_s1 - satellite one tdm decoding fsp correlation weight, real part result of the latest fsp real part correlation. mspw_im_s1 - satellite one tdm decoding fsp correlation weight, imaginary part result of the latest fsp imaginary part correlation. fspphase_s1 - satellite one tdm decoding phase b1-b0 : 00= 0 10= 90 01= 270 11= 180 mfplock_s2 - satellite two tdm decoding status type: singlebyte - r word length: 8 byte name address (hex) bit map reset value (hex) mfpw_re_s1 0220 7-0 -- type: singlebyte - r word length: 8 byte name address (hex) bit map reset value (hex) mfpw_im_s1 0221 7-0 -- type: singlebyte - r word length: 7 byte name address (hex) bit map reset value (hex) fspw_re_s1 0222 6-0 -- type: singlebyte - r word length: 7 byte name address (hex) bit map reset value (hex) fspw_im_s1 0223 6-0 -- type: singlebyte - r word length: 2 byte name address (hex) bit map reset value (hex) fspphase_s1 0224 1-0 -- type: singlebyte - r word length: 7 byte name address (hex) bit map reset value (hex) mfplock_s2 0225 6-0 --
STA400A 70/117 b6-b5 : tdm_sync 00= idle10= fsp resync 01= xmfp hunt11= xmfp resync b4-b3 : tdm_dropout_align 00= idle 10= medium 01= short11= long b2-b1 : tdm_sync_status 00= idle/flush10= sync 01= presync11= unlock b0 : tdm_lock 0= unlock; 1= lock mfplost_s2 - satellite two tdm decoding extended mfp counter number of extended mfp's not found within the synchronization window whilest presynchronized (range from 0 to the value loaded into the register presyncthr_s2, addr:0x0216) or subsequent not found whilest synchro- nized (range from 0 to the value loaded into the register syncthr_s2, addr:0x0217). mfpw_re_s2 - satellite two tdm decoding extended mfp correlation weight, real part result of the latest extended mfp real part correlation. mfpw_im_s2 - satellite two tdm decoding extended mfp correlation weight, imaginary part result of the latest extended mfp imaginary part correlation. fspw_re_s2 - satellite two tdm decoding fsp correlation weight, real part result of the latest fsp real part correlation. type: singlebyte - r word length: 4 byte name address (hex) bit map reset value (hex) mfplost_s2 0226 3-0 -- type: singlebyte - r word length: 8 byte name address (hex) bit map reset value (hex) mfpw_re_s2 0228 7-0 -- type: singlebyte - r word length: 8 byte name address (hex) bit map reset value (hex) mfpw_im_s2 0229 7-0 -- type: singlebyte - r word length: 7 byte name address (hex) bit map reset value (hex) fspw_re_s2 022a 6-0 --
71/117 STA400A mspw_im_s2 - satellite two tdm decoding fsp correlation weight, imaginary part result of the latest fsp imaginary part correlation. fspphase_s2 - satellite two tdm decoding phase b1-b0 : 00= 0 10= 90 01= 270 11= 180 tdmenable_t - terrestrial tdm decoding block enable b4 : terr_tf_en enable sub-block terrestrial tdm fifo b3 : terr_twc_en enable sub-block terrestrial tdm write controller b2 : terr_td_en enable sub-block terrestrial tdm de-scrambling b1 : terr_tt_en enable sub-block terrestrial tdm data formating b0 : terr_ts_en enable sub-block terrestrial tdm synchronization mfplength_t - terrestrial tdm decoding mfp detection window length once the mfp is found, the subsequent appearance is scanned within this symmetric window around the mfp perdicted position on the solf-symbol stream. mfpthrpresync_t - terrestrial tdm decoding mfp detection threshold, pre-synchronization threshold of the mfp correlation determining mfp detection to achieve pre-synchronization if reached or ex- ceeded. type: singlebyte - r word length: 7 byte name address (hex) bit map reset value (hex) fspw_im_s2 022b 6-0 -- type: singlebyte - r word length: 2 byte name address (hex) bit map reset value (hex) fspphase_s2 022c 1-0 -- type: singlebyte - r/w word length: 5 byte name address (hex) bit map reset value (hex) tdmenable_t 022d 4-0 1f type: singlebyte - r/w word length: 4 byte name address (hex) bit map reset value (hex) mfplength_t 022e 3-0 07 type: singlebyte - r/w word length: 7 byte name address (hex) bit map reset value (hex) mfpthrpresync_t 022f 7-0 2c
STA400A 72/117 mfpthrsync_t - terrestrial tdm decoding mfp detection threshold, synchronization threshold of the mfp correlation determining mfp detection to achieve synchronization if reached or exceed- ed. synclength_t - terrestrial tdm synchronization window length number of (predicted) subsequent mfp positions, which are evaluated to determine the status of the mfp syn- chronization. syncthr_t - terrestrial tdm synchronization found threshold number of detected mfps within the tdm decoding synchronization window to achieve synchronization. if this number is not reached or exceeded, the tdm synchronization reenters the initial synchronization procedure searching the mfp on the entire soft-symbol stream. synclost_t - terrestrial tdm synchronization lost threshold number of subsequent undetected mfp's while being synchronized, forcing the tdm synchronization to reenter the initial synchronization procedure searching the mfp on the entire soft-symbol stream. scrambler_t - terrestrial tdm decoding scrambler polinomial dataformat_t - terrestrial tdm decoding data formatting enables swap of data i- and q-component, mcm-map inversion and limiter if the corresponding bit is set. de- type: singlebyte - r/w word length: 7 byte name address (hex) bit map reset value (hex) mfpthrsync_t 0230 7-0 28 type: singlebyte - r/w word length: 5 byte name address (hex) bit map reset value (hex) synclength_t 0231 4-0 03 type: singlebyte - r/w word length: 4 byte name address (hex) bit map reset value (hex) syncthr_t 0232 3-0 02 type: singlebyte - r/w word length: 4 byte name address (hex) bit map reset value (hex) synclost_t 0233 3-0 0b type: multibytes - r/w word length: 12 byte name address (hex) bit map reset value (hex) scrambler2_t 0235 11-8 08 scrambler1_t 0234 7-0 05
73/117 STA400A termines the applied data output format. if the limiter is enabled, data with msb = '1' is replaced by "all-ones", data with msb = '0' is shifted left logically. b3 : map_inv b2 : format 0= two's complement; 1= offset binary b1 : limit b0 : iq_swap tdmstatus_t - terrestrial tdm decoding status b2-b1 : tdm_sync_status 00= idle 10= sync 01= presync 11= unlock b0 : tdm_lock 0 = unlock 1= lock mfplost_t - terrestrial tdm decoding mfp correlation lost number of mfps found within the synchronization window whilest pre-synchronized (range from 0 to the value loaded into the register synclost_t, addr:0x0233). mfpw_re_t - terrestrial tdm decoding mfp correlation weight, real part result of the latest mfp real part correlation. mfpw_im_t - terrestrial tdm decoding mfp correlation weight, imaginary part result of the latest mfp imaginary part correlation. type: singlebyte - r/w word length: 4 byte name address (hex) bit map reset value (hex) dataformat_t 0236 3-0 00 type: singlebyte - r word length: 3 byte name address (hex) bit map reset value (hex) tdmstatus_t 0237 2-0 -- type: singlebyte - r word length: 4 byte name address (hex) bit map reset value (hex) mfplost_t 0239 3-0 -- type: singlebyte - r word length: 8 byte name address (hex) bit map reset value (hex) mfpw_re_t 023a 7-0 -- type: singlebyte - r word length: 8 byte name address (hex) bit map reset value (hex) mfpw_im_t 023b 7-0 --
STA400A 74/117 tdmphase_t - terrestrial tdm decoding phase b1-b0 : 00= 0 10= 90 1= 270 11= 180 tdmsyncctrl_t - terrestrial tdm decoding synchronization control b0 : fsm_fallback_en swfgenable_s - satellite weighting factor generation block enable b7 : swfg2_fsp_invalid_en enable satellite two weighting factor generation fsp invalid evalutation.weights are forced to '0' if this bit is set to '1' and the tdm decode block detects an invalid fsp. b6 : swfg2_cycle_slip_en enable satellite two weighting factor generation cycle slip evalutation. weights are forced to '0' if this bit is set to '1' and the tdm decode block detects a cycle slip. b5 : swfg2_fifo_en enable sub-block satellite two weighting factor fifo b4 : swfg2_comp_en enable sub-block satellite two weighting factor calculation b3 : swfg1_fsp_invalid_en enable satellite one weighting factor generation fsp invalid evalutation.weights are forced to '0' if this bit is set to '1' and the tdm decode block detects an invalid fsp. b2 : swfg1_cycle_slip_en enable satellite one weighting factor generation cycle slip evalutation. weights are forced to '0' if this bit is set to '1' and the tdm decode block detects a cycle slip. b1 : swfg1_fifo_en enable sub-block satellite one weighting factor fifo b0 : swfg1_comp_en enable sub-block satellite one weighting factor calculation type: singlebyte - r word length: 2 byte name address (hex) bit map reset value (hex) tdmphase_t 023c 1-0 -- type: singlebyte - r/w word length: 1 byte name address (hex) bit map reset value (hex) tdmsyncctrl_t 023f 0 01 type: singlebyte - r/w word length: 7 byte name address (hex) bit map reset value (hex) swfg_enable_s 0240 7-0 ff
75/117 STA400A swfgstatus_s - satellite weighting factor generation status b1 : swfg2_status sat2 weighting factor generation status 0=idle1=operational b0 : swfg1_status sat1 weighting factor generation status 0=idle1=operational prc_en - tdm prc interface block enable b2-b1 : prc source 00= satellite1 10= terrestrial 01= satellite2 11= rfu b0 : block_en 0= disabled 1= enabled prc_num - prc number this register sets the prc number in the range from 1 to 258. descdataen - signal selection for multiplexer after descrambler select signals for multiplexer after tdm descrambling (0: original data; 1: register contents) b4 : swfg2_data_out_en b3 : swfg1_data_out_en b2 : sat2_data_out_en b1 : sat1_data_out_en b0 : terr_data_out_en type: singlebyte - r word length: 2 byte name address (hex) bit map reset value (hex) swfgstatus_s 0241 1-0 -- type: singlebyte - r/w word length: 3 byte name address (hex) bit map reset value (hex) prc_en 0250 2-0 00 type: multibyte2 - r/w word length: 9 byte name address (hex) bit map reset value (hex) prc_num2 0252 8 00 prc_num1 0251 7-0 00 type: singlebyte - r/w word length: 5 byte name address (hex) bit map reset value (hex) descdataen 0260 4-0 00
STA400A 76/117 descdata_re_t - terrestrial test real data descdata_im_t - terrestrial test imaginary data descdata_re_s1 - sat1 test real data descdata_im_s1 - sat1 test imaginary data descdata_re_s2 - sat2 test real data descdata_im_s2 - sat2 test imaginary data descdata_s1wfg - sat1 weighting test data type: singlebyte - r/w word length: 8 byte name address (hex) bit map reset value (hex) descdata_re_t 0261 7-0 00 type: singlebyte - r/w word length: 8 byte name address (hex) bit map reset value (hex) descdata_im_t 0262 7-0 00 type: singlebyte - r/w word length: 4 byte name address (hex) bit map reset value (hex) descdata_re_s1 0263 3-0 00 type: singlebyte - r/w word length: 4 byte name address (hex) bit map reset value (hex) descdata_im_s1 0264 3-0 00 type: singlebyte - r/w word length: 4 byte name address (hex) bit map reset value (hex) descdata_re_s2 0265 3-0 00 type: singlebyte - r/w word length: 4 byte name address (hex) bit map reset value (hex) descdata_im_s2 0266 3-0 00 type: singlebyte - r/w word length: 4 byte name address (hex) bit map reset value (hex) descdata_s1wfg 0267 3-0 00
77/117 STA400A descdata_s2wfg - sat2 weighting test data tpmenable_s - satellite tdm preamble monitor enable b1 : tpm2_en enable sub-block satellite two tdm preamble monitor b0 : tpm1_en enable sub-block satellite one tdm preamble monitor tpmdataformat_s1 - sat1 tdm preamble monitor input data format control swap of i- and q-component and data inversion for input data. if one bit is set to '1' it's corresponding functionality is invoked. b1 : tpm_invert_data_in b0 : tpm_iq_swap_data_in tpmmfpthr_s1 - sat1 tdm preamble monitor mfp detection threshold threshold of the mfp correlation determining mfp detection if reached or exceeded. tpmfspthr_s1 - sat1 tdm preamble monitor fsp detection threshold threshold of the fsp correlation determining fsp detection if reached or exceeded. tpmdataformat_s2 - sat2 tdm preamble monitor input data format control swap of i- and q-component and data inversion for input data. if one bit is set to '1' it's corresponding type: singlebyte - r/w word length: 4 byte name address (hex) bit map reset value (hex) descdata_s2wfg 0268 3-0 00 type: singlebyte - r/w word length: 2 byte name address (hex) bit map reset value (hex) tpmenable_s 0280 1-0 00 type: singlebyte - r/w word length: 2 byte name address (hex) bit map reset value (hex) tpmdataformat_s1 0281 1-0 00 type: singlebyte - r/w word length: 7 byte name address (hex) bit map reset value (hex) tpmmfpthr_s1 0282 6-0 28 type: singlebyte - r/w word length: 6 byte name address (hex) bit map reset value (hex) tpmfspthr_s1 0283 5-0 14
STA400A 78/117 functionality is invoked. b1 : tpm_invert_data_in b0 : tpm_iq_swap_data_in tpmmfpthr_s2 - sat2 tdm preamble monitor mfp detection threshold threshold of the mfp correlation determining mfp detection if reached or exceeded. tpmfspthr_s2 - sat2 tdm preamble monitor fsp detection threshold threshold of the fsp correlation determining fsp detection if reached or exceeded. tpmmfpw_re_s1 - sat1 tdm preamble monitor mfp correlation weight, real part result of the latest mfp real part correlation. tpmmfpw_im_s1 - sat1 tdm preamble monitor mfp correlation weight, imaginary part result of the latest mfp imaginary part correlation. tpmmfpsymslip_s1 - sat1 tdm preamble monitor mfp symbol slip type: singlebyte - r/w word length: 2 byte name address (hex) bit map reset value (hex) tpmdataformat_s2 0284 1-0 00 type: singlebyte - r/w word length: 7 byte name address (hex) bit map reset value (hex) tpmmfpthr_s2 0285 6-0 28 type: singlebyte - r/w word length: 6 byte name address (hex) bit map reset value (hex) tpmfspthr_s2 0286 5-0 14 type: singlebyte - r word length: 8 byte name address (hex) bit map reset value (hex) tpmmfpw_re_s1 0290 7-0 -- type: singlebyte - r word length: 8 byte name address (hex) bit map reset value (hex) tpmmfpw_im_s1 0291 7-0 -- type: multibytes - r word length: 12 byte name address (hex) bit map reset value (hex) tpmmfpsymslip2_s1 0293 11-8 -- tpmmfpsymslip1_s1 0292 7-0 --
79/117 STA400A tpmfspw_re_s1 - sat1 tdm preamble monitor fsp correlation weight, real part result of the latest fsp real part correlation. tpmfspw_im_s1 - sat1 tdm preamble monitor fsp correlation weight, imaginary part result of the latest fsp imaginary part correlation. tpmfspposslip_s1 - sat1 tdm preamble monitor fsp position slip tpmfsptdmphase_s1 - sat1 tdm preamble monitor fsp phase phase of the tdm soft-symbol stream basing the result on the lastest fsp correlation. b1-b0 : 00= 010= 90 01= 27011= 180 tpmprdetect_s1 - sat1 tdm preamble monitor preamble detection preamble detection based on the result of the latest preamble correlation. tpmfspcyslipcnt_s1 - sat1 tdm preamble monitor fsp cycle slip counter cycle slip counter based on fsp evaluation whilst fsp detected for the latest tdm frame. type: singlebyte - r word length: 7 byte name address (hex) bit map reset value (hex) tpmfspw_re_s1 0294 6-0 -- type: singlebyte - r word length: 7 byte name address (hex) bit map reset value (hex) tpmfspw_im_s1 0295 6-0 -- type: multibytes - r word length: 12 byte name address (hex) bit map reset value (hex) tpmfspposslip2_s1 0297 11-8 -- tpmfspposslip1_s1 0296 7-0 -- type: singlebyte - r word length: 2 byte name address (hex) bit map reset value (hex) tpmfsptdmphase_s1 0298 1-0 -- type: singlebyte - r word length: 2 byte name address (hex) bit map reset value (hex) tpmprdetect_s1 0299 1-0 -- type: singlebyte - r word length: 8 byte name address (hex) bit map reset value (hex) tpmfspcyslipcnt_s1 029a 7-0 --
STA400A 80/117 tpmfspposlipcnt_s1 - sat1 tdm preamble monitor fsp position slip counter fsp position slip counter based on the distorsion of the detected fsps to their expected position with respect to the lastest detected mfp. tpmmfpw_re_s2 - sat2 tdm preamble monitor mfp correlation weight, real part result of the latest mfp real part correlation. tpmmfpw_im_s2 - sat2 tdm preamble monitor mfp correlation weight, imaginary part result of the latest mfp imaginary part correlation. tpmmfpsymslip_s2 - sat2 tdm preamble monitor mfp symbol slip tpmfspw_re_s2- sat2 tdm preamble monitor fsp correlation weight, real part result of the latest fsp real part correlation. tpmfspw_im_s2- sat2 tdm preamble monitor fsp correlation weight, imaginary part result of the latest fsp imaginary part correlation. type: singlebyte - r word length: 8 byte name address (hex) bit map reset value (hex) tpmfspposlipcnt_s1 029b 7-0 -- type: singlebyte - r word length: 8 byte name address (hex) bit map reset value (hex) tpmmfpw_re_s2 02a0 7-0 -- type: singlebyte - r word length: 8 byte name address (hex) bit map reset value (hex) tpmmfpw_im_s2 02a1 7-0 -- type: multibytes - r word length: 12 byte name address (hex) bit map reset value (hex) tpmmfpsymslip2_s2 02a3 11-8 -- tpmmfpsymslip1_s2 02a2 7-0 -- type: singlebyte - r word length: 7 byte name address (hex) bit map reset value (hex) tpmfspw_re_s2 02a4 6-0 -- type: singlebyte - r word length: 7 byte name address (hex) bit map reset value (hex) tpmfspw_im_s2 02a5 6-0 --
81/117 STA400A tpmfspposslip_s2 - sat2 tdm preamble monitor fsp position slip tpmfsptdmphase_s2 - sat2 tdm preamble monitor fsp phase phase of the tdm soft-symbol stream basing the result on the lastest fsp correlation. b1-b0 : 00= 0 10= 90 01= 270 11= 180 tpmprdetect_s2 - sat2 tdm preamble monitor preamble detection preamble detection based on the result of the latest preamble correlation. tpmfspcyslipcnt_s2 - sat2 tdm preamble monitor fsp cycle slip counter cycle slip counter based on fsp evaluation whilst fsp detected for the latest tdm frame. tpmfspposlipcnt_s2 - sat2 tdm preamble monitor fsp position slip counter fsp position slip counter based on the distorsion of the detected fsps to their expected position with respect to the lastest detected mfp. type: multibytes - r word length: 12 byte name address (hex) bit map reset value (hex) tpmfspposslip2_s2 02a7 11-8 -- tpmfspposslip1_s2 02a6 7-0 -- type: singlebyte - r word length: 2 byte name address (hex) bit map reset value (hex) tpmfsptdmphase_s2 02a8 1-0 -- type: singlebyte - r word length: 2 byte name address (hex) bit map reset value (hex) tpmprdetect_s2 02a9 1-0 -- type: singlebyte - r word length: 8 byte name address (hex) bit map reset value (hex) tpmfspcyslipcnt_s2 02aa 7-0 -- type: singlebyte - r word length: 8 byte name address (hex) bit map reset value (hex) tpmfspposlipcnt_s2 02ab 7-0 --
STA400A 82/117 tpmsyslip_s1 - sat1 tdm decoding symbol slip extended mfp detection based symbol slip. tpmsyslip_s2 - sat2 tdm decoding symbol slip extended mfp detection based symbol slip. tpmsyslip_t - terrestrial tdm decoding symbol slip fspstartwinlen_s1 - sat1 tdm decoding fsp detection start window length entering a short range dropout condition, the fsp is searched within a symetrical (start) window around the nominal fsp position. fsphuntwininc_s1 - sat1 tdm decoding fsp detection hunt window increment entering a medium range dropout condition, the fsp is searched within a symetrical window around the nominal fsp position. this window is increased on fsp period bases with an increment of inc/8 symbols begining with the start window length. type: multibytes - r word length: 12 byte name address (hex) bit map reset value (hex) tpmsyslip2_s1 02b1 11-8 -- tpmsyslip1_s1 02b0 7-0 -- type: multibytes - r word length: 12 byte name address (hex) bit map reset value (hex) tpmsyslip2_s2 02b3 11-8 -- tpmsyslip1_s2 02b2 7-0 -- type: multibytes - r word length: 10 byte name address (hex) bit map reset value (hex) tpmsyslip2_t 02b5 9-8 -- tpmsyslip1_t 02b4 7-0 -- type: singlebyte - r/w word length: 3 byte name address (hex) bit map reset value (hex) fspstartwinlen_s1 02c0 2-0 02 type: singlebyte - r/w word length: 4 byte name address (hex) bit map reset value (hex) fsphuntwininc_s1 02c1 3-0 03
83/117 STA400A fspshdropoutlen_s1 - sat1 tdm decoding fsp short dropout length number of subsequent undetected fsps determining the upper limit of a short range dropout condition. fspsecualignthr_s1 - sat1 tdm decoding fsp secure alignment threshold number of subsequent detected fsps with nominal fsp period length determining secure alignment to the tdm soft-symbol stream within a medium range dropout condition. fspstartwinlen_s2 - sat2 tdm decoding fsp detection start window length entering a short range dropout condition, the fsp is searched within a symetrical (start) window around the nominal fsp position. fsphuntwininc_s2 - sat2 tdm decoding fsp detection hunt window increment entering a medium range dropout condition, the fsp is searched within a symetrical window around the nominal fsp position. this window is increased on fsp period bases with an increment of inc/8 symbols begining with the start window length. fspshdropoutlen_s2 - sat2 tdm decoding fsp short dropout length number of subsequent undetected fsps determining the upper limit of a short range dropout condition. fspsecualignthr_s2 - sat2 tdm decoding fsp secure alignment threshold number of subsequent detected fsps with nominal fsp period length determining secure alignment to the type: singlebyte - r/w word length: 5 byte name address (hex) bit map reset value (hex) fspshdropoutlen_s1 02c2 4-0 0f type: singlebyte - r/w word length: 3 byte name address (hex) bit map reset value (hex) fspsecualignthr_s1 02c3 2-0 03 type: singlebyte - r/w word length: 3 byte name address (hex) bit map reset value (hex) fspstartwinlen_s2 02c8 2-0 02 type: singlebyte - r/w word length: 4 byte name address (hex) bit map reset value (hex) fsphuntwininc_s2 02c9 3-0 03 type: singlebyte - r/w word length: 5 byte name address (hex) bit map reset value (hex) fspshdropoutlen_s2 02ca 4-0 0f
STA400A 84/117 tdm soft-symbol stream within a medium range dropout condition. 2.5 fec control_f - fec control register the control flags enable the corresponding operation if set, otherwise the operation is disabled. the flags fec_en and fec_prep enable the operation of the fec and fec preprocessing. weighting of the two satellite data streams is performed only when wgt_en=1, otherwise the data from the memory are not weighted. the flags terr_format and sat_format determine the viterbi input data format for both terrestrial and satellite data streams. as only one viterbi decoder is applied both flags have to be equal. the viterbi flush operation is enabled at the end of a prc packet when vd_flush_on=1. b5 : vd_flush_on 0= vd flush disabled 1= vd flush enabled b4 : sat_format 0= satellite data in twos complement (viterbi input) 1= satellite data in offset binary (viterbi input) b3 : terr_format 0= terrstrial data in twos complement (viterbi input) 1= terrestrial data in offset binary (viterbi input) b2 : wgt_en 0= satellite weighting disabled 1= satellite weighting enabled b1 : fec_prep_en 0= fec preprocessing disabled 1= fec preprocessing enabled b0 : fec_en 0= fec disabled 1= fec enabled status_f - fec status register the status vector comprises the status flags of the sub-modules of the fec processing. an inactive module is indicated by status=0, an active module by status=1 b3 : fec preprocessing 0= fec preprocessing inactive type: singlebyte - r/w word length: 3 byte name address (hex) bit map reset value (hex) fspsecualignthr_s2 02cb 2-0 03 type: singlebyte - r/w word length: 6 byte name address (hex) bit map reset value (hex) control_f 0300 5-0 3f type: singlebyte - r word length: 4 byte name address (hex) bit map reset value (hex) status_f 0301 3-0 --
85/117 STA400A 1= fec preprocessing operational b2 : rs input control 0= rs input control inactive 1= rs input control operational b1 : viterbi decoder 0= vd inactive 1= vd operational b0 : fec management 0= fec management inactive 1= fec management operational errorctrl_f - fec error register b5-b0 : 0x00 -> asynchronous status overwrite for each prc proceed 0x01 -> update fec error registers with tscc1 status only 0x02 -> update fec error registers with tscc2 status only 0x03 -> update fec error registers with 1 st prc packet after tsccs ... 0x32 -> update fec error registers with 48 th prc packet after tsccs x33-0x3f -> undefined initstate_f - convolutional decoder initial state control register initial state of convolutional decoder after training sequence, which corresponds to the reverse of the last 6 bits of the prc preamble 1d(hex)=00011101 -> 101110 = 2e(hex)=46(dec). initlfsr_f - viterbi decoder lfsr initial state type: singlebyte - r/w word length: 6 byte name address (hex) bit map reset value (hex) errorctrl_f 0302 5-0 01 type: singlebyte - r/w word length: 6 byte name address (hex) bit map reset value (hex) initstate_f 0307 5-0 2e type: multibytes - r/w word length: 12 byte name address (hex) bit map reset value (hex) initlfsr2_f 0309 11-8 0c initlfsr1_f 0308 7-0 cc
STA400A 86/117 initterm_f - termination sequence after flush operation sequence after flush operation for termination of viterbi decoder. the upper 8 bits have to be the prc preamble 1d(hex) in ascending order (b12..b19). vitberctrl_f - viterbi ber measurements control b3 : fvd_csat_ber_mode 0= sat. measurment as single acquisition 1= sat. measurement as continuous acquisition b2 : fvd_csat_ber_en 0= sat. ber measurement disabled 1= sat ber measurement enabled b1 : fvd_terr_ber_mode 0= terr. measurment as single acquisition 1= terr. measurement as continuous acquisition b0 : fvd_terr_ber_en 0= terr. ber measurement disabled 1= terr. ber measurement enabled terrber_f - terrestrial channel bit error rate the terrestrial channel error rate states the number of channel symbol errors which where determined within one prc packet by reencoding of the viterbi-decoded terrestrial data stream. a new measurement is indicated by the signal terr_ber_done which is comprised in the interrupt vector (addr. 0x0350) sat1ber_f - satellite 1 channel bit error rate the sat1 channel error rate states the number of channel symbol errors which where determined within one prc packet by reencoding of the viterbi-decoded sat1 data stream. a new measurement is indicated by the type: multibytes - r/w word length: 20 byte name address (hex) bit map reset value (hex) initterm3_f 030c 19-16 0b initterm2_f 030b 15-8 80 initterm1_f 030a 7-0 00 type: singlebyte - r/w word length: 4 byte name address (hex) bit map reset value (hex) vitberctrl_f 0310 3-0 0f type: multibytes - r word length: 12 byte name address (hex) bit map reset value (hex) terrber2_f 0321 11-8 -- terrber1_f 0320 7-0 --
87/117 STA400A signal sat1_ber_done which is comprised in the interrupt vector (addr. 0x0350) sat2ber_f - satellite 2 channel bit error rate the sat2 channel error rate states the number of channel symbol errors which where determined within one prc packet by reencoding of the viterbi-decoded sat2 data stream. a new measurement is indicated by the signal sat2_ber_done which is comprised in the interrupt vector (addr. 0x0350) forcecorr_f - fec control register this register is used to force the correction value for prc preamble (system value 0x1d) at rs input rs_ctrl_f - rs decoder configuration b3-b2 : rs error count conf 00= count 16 rs blocks (8 prcs); 01= count 64 rs blocks (32 prcs); 10= count 256 rs blocks (128 prcs); 11= count 1024 rs blocks (512 prcs). b1 : terr_csat_comb 1= enable terrestrial-satellite combining 0= disable terrestrial-satellite combining b0 : force_corr_en 1= enable forced correction of prc preamble; 0= disable forced correction of prc preamble rs_cnt_f - rs decoder error count control this register controls the rs error counter. after reset the counter is disabled. to start ber measurement a value must be written in this register. when written, this register generates a one clock cycle trigger signal for type: multibytes - r word length: 12 byte name address (hex) bit map reset value (hex) sat1ber2_f 0325 11-8 -- sat1ber1_f 0324 7-0 -- type: multibytes - r word length: 12 byte name address (hex) bit map reset value (hex) sat2ber2_f 0329 11-8 -- sat2ber1_f 0328 7-0 -- type: singlebyte - r/w word length: 8 byte name address (hex) bit map reset value (hex) forcecorr_f 0330 7-0 1d type: singlebyte - r/w word length: 4 byte name address (hex) bit map reset value (hex) rs_ctrl_f 0331 3-0 03
STA400A 88/117 the rs error counter. b0 : error counter control 0= continuos acquisition; 1= single acquisition. rs_bytecnt_f - rs byte corrected error counter this register is 14 bits long and is divided into two bytes. the lsb byte is named rs _bytecnt1, the msb byte is named rs_bytecnt2. it cointains the number of the corrected rs bytes with unsigned format. rs_framecnt_f - corrupted rs block counter this register is 10 bits long and is divided into two bytes. the lsb byte is named rs _framecnt1, the msb byte is named rs _framecnt2. it cointains the number of the corrupted rs blocks with unsigned format. initseq_f - viterbi decoder initialization sequence the viterbi decoder is initialized with the prc preamble (hex 1d) rs1_terrbyteerr_f - terrestrial rs block1 error register b4-b0 : 0x00 -> no errors type: singlebyte - wrt word length: 1 byte name address (hex) bit map reset value (hex) rs_cnt_f 0332 0 01 type: multibytes - r word length: 14 byte name address (hex) bit map reset value (hex) rs_bytecnt2_f 0336 13-8 -- rs_bytecnt1_f 0335 7-0 -- type: multibytes - r word length: 10 byte name address (hex) bit map reset value (hex) rs_framecnt2_f 0338 9-8 -- rs_framecnt1_f 0337 7-0 -- type: singlebyte - r/w word length: 8 byte name address (hex) bit map reset value (hex) initseq_f 0340 7-0 1d type: singlebyte - r word length: 5 byte name address (hex) bit map reset value (hex) rs1_terrbyteerr_f 0342 4-0 --
89/117 STA400A 0x01 -> 1 byte error corrected 0x02 -> 2 byte errors corrected ... 0x10 -> 16 byte errors corrected 0x1f -> uncorrectable errors rs2_terrbyteerr_f - terrestrial rs block2 error register b4-b0 : 0x00 -> no errors 0x01 -> 1 byte error corrected 0x02 -> 2 byte errors corrected ... 0x10 -> 16 byte errors corrected 0x1f -> uncorrectable errors rs1_satbyteerr_f - satellite rs block1 error register b4-b0 : 0x00 -> no errors 0x01 -> 1 byte error corrected 0x02 -> 2 byte errors corrected ... 0x10 -> 16 byte errors corrected 0x1f -> uncorrectable errors rs2_satbyteerr_f - satellite rs block2 error register b4-b0 : 0x00 -> no errors 0x01 -> 1 byte error corrected 0x02 -> 2 byte errors corrected type: singlebyte - r word length: 5 byte name address (hex) bit map reset value (hex) rs2_terrbyteerr_f 0343 4-0 -- type: singlebyte - r word length: 5 byte name address (hex) bit map reset value (hex) rs1_satbyteerr_f 0344 4-0 -- type: singlebyte - r word length: 5 byte name address (hex) bit map reset value (hex) rs2_satbyteerr_f 0345 4-0 --
STA400A 90/117 ... 0x10 -> 16 byte errors corrected 0x1f -> uncorrectable errors rs_block_decis_f - status of the last rs diversity decision b1-b0 : 00 = satellite path selected for current frame 01 = terrestrial path selected for current frame 10 = undefined 01 = undefined irqmask_f - fec interrupt mask this register masks the interrupt request when a 0 is written in the relative bit. b4 : interrupt mask for rs_cnt_end b3 : interrupt mask for sat2_ber_done b2 : interrupt mask for sat1_ber_done b1 : interrupt mask for terr_ber_done b0 : interrupt mask for fec_irq_status irqstatus_f - fec interrupt status this is the interrupt status vector. when a bit means that an interrupt is requested by the corresponding block. to reset a single bit, a 0 must be written into. 0x00 resets the complete vector. b4 : rs_cnt_end interrupt for new rs error count measurement b3 : sat2_ber_done interrupt for new sat2 ber measurement sat2_ber b2 : sat1_ber_done interrupt for new sat1 ber measurement sat1_ber b1 : terr_ber_done interrupt for new terr. ber measurement terr_ber b0 : fec_irq_status interrupt signal from fec management type: singlebyte - r word length: 2 byte name address (hex) bit map reset value (hex) rs_status_decis_f 0346 1-0 -- type: singlebyte - int word length: 5 byte name address (hex) bit map reset value (hex) irqmask_f 0350 4-0 00 type: singlebyte - int word length: 5 byte name address (hex) bit map reset value (hex) irqstatus_f 0351 4-0 00
91/117 STA400A 2.6 if sampling and control interface agc_ctrl1 - agc control register #1 this register controls terrestrial and satellite agc loop gain and the sense of the tagc and sagc control pins. b7 : tagcchs terrestrial agc loop change sign b6-b4 : tagcbeta(2:0) terrestrial agc loop gain. b3 : sagcchs satellite agc loop change sign b2-b0 : sagcbeta(2:0) satellite agc loop gain. sagcref - satellite agc reference level this register is 13 bits long and is divided into two bytes. the lsb byte is named sagcref0, the msb byte is named sagcref1. it sets the signal level at the satellite adc input. sagcintg - satellite agc integrator this register is connected to the 8msb of the internal integrator of the satellite agc loop. it gives an image of the power level at the satellite analog input. the register format is twos complement. type: singlebyte - r/w word length: 8 byte name address (hex) bit map reset value (hex) agc_ctrl1 0400 7-0 88 tagcbeta and sagcbeta gain table: tagcbeta/ sagcbeta loop gain 000 2**0 = 1 001 2**1 = 2 010 2**2 = 3 011 2**3 = 4 100 2**4 = 16 101 2**5 = 32 110 2**6 = 64 111 open loop type: multibytes - r/w word length: 13 byte name address (hex) bit map reset value (hex) sagcref1 0402 12-8 01 sagcref0 0401 7-0 90 type: singlebyte - r/w word length: 8 byte name address (hex) bit map reset value (hex) sagcintg 0403 7-0 00
STA400A 92/117 tagcref - terrestrial agc reference level this register is 13 bits long and is divided into two bytes. the lsb byte is named tagcref0, the msb byte is named tagcref1. it sets the signal level at the terrestrial adc input. tagcintg - terrestrial agc integrator this register is connected to the 8msb of the internal integrator of the terrestrial agc loop. it gives an image of the power level at the terrestrial analog input. the register format is twos complement. if_ctrl - if sampling control register this register selects the external adc format and controls the average filter of the agc integrator. b7 : avg_off internal averager circuit disable. 1=averager disabled; 0=averager enabled. b6-b2 : reserved for future use b1 : format external/internal adc code format. 1=twos complement; 0=offset binary. b0 :reserved seltstout - internal test bus selection for each block this register selects, for each internal blocks, which signals are connected to the ftestout pins. it must ve used together with the tstmuxctl register (addr 0x040b). b3-b0 :tbd tstmuxctl - selection of the internal block for functional test this register selects, among 16 test buses from the internal functional blocks, the one to be connected to the ftestout bus according with the table below. it must ve used together with the seltstout register (addr type: multibytes - r/w word length: 13 byte name address (hex) bit map reset value (hex) tagcref1 0405 12-8 01 tagcref0 0404 7-0 90 type: singlebyte - r/w word length: 8 byte name address (hex) bit map reset value (hex) tagcintg 0406 7-0 00 type: singlebyte - r/w word length: 8 byte name address (hex) bit map reset value (hex) if_ctrl 0407 7-0 00 type: singlebyte - r/w word length: 4 byte name address (hex) bit map reset value (hex) seltstout 040a 3-0 00
93/117 STA400A 0x040a). b3-b0 : 0000 reserved 0001 reserved 0010 reserved for future use 0011 reserved for future use 0100 reserved for future use 0101 pc bitstream interface #2 0110 pc bitstream interface #1 0111 fec_rs (reed-solomon decoder) 1000 fec_fpp (fec pre-processing) 1001 fec_vd 1010 tdm 1011 reserved for future use 1100 terrestrial demodulator (mcm demodulator) 1101 satellite demodulator #2 (qpsk2) 1110 satellite demodulator #1 (qpsk1) 1111 if sampling clkdiv_conf - master clock programmable divider this register sets the division factor (2,4 or 8) of the master clock applied to xti/mclk input. the divided clock is available at clkd output (pin 56). b1 - b0 : clk_div 00 = mclk/2 (clkd frequency = 23.92mhz/2=11.96mhz) 01 = mclk/4 (clkd frequency = 23.92mhz/2=11.96mhz) 10 = mclk/8 (clkd frequency = 23.92mhz/2=11.96mhz) 11 = disabled (clkd fixed to gnd) qpsk_ber_ctrl - satellite demodulators ber control this register is used in functional test mode for b.e.r. measurement after satellite demodulation, using an ex- ternal serial ber tester. the ber measurement is on the hard decided output symbol and the relative clock available at the ftestout interface (see seltstout register description). this register controls the interface operations to synchronize the ber tester on the demodulated satellite sym- type: singlebyte - r/w word length: 4 byte name address (hex) bit map reset value (hex) tstmuxctl 040b 3-0 00 type: singlebyte - r/w word length: 2 byte name address (hex) bit map reset value (hex) clkdiv_conf 040c 1-0 03
STA400A 94/117 bols before starting the ber computation. b2 : iq swap swap between i and q components of the received symbols b1 - b0 : phchg phase ambiguity correction 00 = 0 degrees 01 = 90 degrees 10 = 180 degrees 11 = 270 degrees control - general purpose control register this register controls the master clock outputs, the bidirectional buses mode to access the external memory and the bist access mode (reserved for structural test). b7 : mclko_off mclko output buffer disable. 0 = buffer active; 1 = buffer disabled (output fixed to ground). b6 : mclkon_off mclkon output buffer disable. 0 = buffer active; 1 = buffer disabled (output fixed to ground). b5 : mdqm_ctrl external memory input/output mask polarity. 0 = high level active; 1 = low level active. b4-b1 : reserved b0 : irq_rst_ctrlreset after read on the interrupt register (irq1_status) 0 = disabled; 1 = enabled. irq1_mask - interrupt mask register enable/disable interrupts on intr pin. type: singlebyte - r/w word length: 3 byte name address (hex) bit map reset value (hex) qpsk_ber_ctrl 040d 2-0 00 type: singlebyte - r/w word length: 8 byte name address (hex) bit map reset value (hex) control 0410 7-0 00 type: singlebyte - r/w word length: 8 byte name address (hex) bit map reset value (hex) irq1_mask 0417 7-0 00
95/117 STA400A b7 : sat2 lock indicator interrupt masked 0=disabled; 1=enabled. b6 : sat1 lock indicator interrupt masked 0=disabled; 1=enabled. b5 : mfp_clk interrupt masked (5 msec impulse sync) 0=disabled; 1=enabled. b4 : mfp_clk interrupt masked (level) 0=disabled; 1=enabled. b3 : iic-bus illegal address masked 0=disabled; 1=enabled. b2 : tdm interrupt masked 0=disabled; 1=enabled. b1 : fec interrupt masked 0=disabled; 1=enabled. b0 : mcm interrupt masked 0=disabled; 1=enabled. note : bit5 and bit4 cannot be used togheter, i.e. if bit5 is used the bit4 must be masked and viceversa. if both are enabled, bit4 will be sent to intr pin. irq1_status - interrupt status register this register represents the interrupt vector when the intr pin is activated (high level active). it can be reset after read if the bit0 (irq_rst_ctrl) of the control register is set to 1 or a single bit can be reset directly writing 0. b7 : interrupt request from sat2 lock indicator (high active); b6 : interrupt request from sat1 lock indicator (high active); b5 : interrupt request from mfp_clk (5 msec impulse continuos sync signal); bit5 is generated from the mfp_clk and is a 432msec period signal with ~1.16% duty-cycle (5msec/432msec); there is no need to reset bit5 by the interrupt routine. b4 : interrupt request from mfp_clk (high active). bit4 is activated by the positive edge of the mfp_clk and is a high level signal; the interrupt routing must reset this bit. b3 : interrupt request from iic-bus illegal address (high active); b2 : interrupt request from tdm (high active); b1 : interrupt request from fec (high active); b0 : interrupt request from mcm (high active). status1 - cdec status register this register represents the interrupt vector when the intr pin is activated (high level active). it can be reset after read if the bit0 (irq_rst_ctrl) of the control register is set to 1 or a single bit can be reset directly writing 0. b7-b4 : reserved for future use type: singlebyte - pr word length: 8 byte name address (hex) bit map reset value (hex) irq1_status 0419 7-0 00 type: singlebyte - r word length: 8 byte name address (hex) bit map reset value (hex) status1 041f 7-0 --
STA400A 96/117 b4 : terrestrial demodulator lock indicator 0 = locked 1 = unlocked b3 : satellite #2 lock indicator 0 = locked 1 = unlocked b2 : satellite #1 lock indicator 0 = locked 1 = unlocked b1 : fec terrestrial-satellite combining decision for rs block #2 0 = satellite; 1 = terrestrial; b0 : fec terrestrial-satellite combining decision for rs block #1 0 = satellite; 1 = terrestrial; 2.7 pc bitstream interface pcdc_conf_0 - clock configuration for pc interface #0 b6-b2 : pcdc_divvalue_0 master clock divider. the master clock is divided by ( pcdc _ divvalue _0+1)*2. b1 : pcdc_neg_0 1=pcdc0 is inverted. b0 : pcdc_runfree_0 0=clock running only when data is sent out; 1=clock always running. pcdc_conf_1 - clock configuration for pc interface #1 b6-b2 : pcdc_divvalue_1 master clock divider. the master clock is divided by ( pcdc _ divvalue _1+1)*2. b1 : pcdc_neg_11=pcdc0 is inverted. b0 : pcdc_runfree_10=clock running only when data is sent out; 1=clock always running. pcsd_conf_0 - data configuration for pc interface #0 b5-b4 : pcsd_fflagmode_0 00=frame flag bit is always set to 0; 01=frame flag bit is set to 1 only for the first byte of tscc1; 10=frame flag bit is set to 1 for the first byte of all prcs; type: singlebyte - r/w word length: 7 byte name address (hex) bit map reset value (hex) pcdc_conf_0 0500 6-0 00 type: singlebyte - r/w word length: 7 byte name address (hex) bit map reset value (hex) pcdc_conf_1 0501 6-0 00 type: singlebyte - r/w word length: 6 byte name address (hex) bit map reset value (hex) pcsd_conf_0 0502 5-0 00
97/117 STA400A 11=frame flag bit is set to 1 for the first byte of all prcs. b3 : pcsd_frameflag_0 1=frame flag bit is appended to each data byte b2 : pcsd_oddparity_0 0=even parity bit is generated; 1=odd parity bit is generated. b1 : pcsd_addparity_0 1=parity bit is appended to each data. b0 : pcsd_lsbfirst_0 0=parallel data sent out msb first; 1=parallel data sent out lsb first. pcsd_conf_1 - data configuration for pc interface #1 b5-b4 : pcsd_fflagmode_1 00=frame flag bit is always set to 0; 01=frame flag bit is set to 1 only for the first byte of tscc1; 10=frame flag bit is set to 1 for the first byte of all prcs; 11=frame flag bit is set to 1 for the first byte of all prcs. b3 : pcsd_frameflag_1 1=frame flag bit is appended to each data byte. b2 : pcsd_oddparity_1 0=even parity bit is generated; 1=odd parity bit is generated. b1 : pcsd_addparity_1 1=parity bit is appended to each data. b0 : pcsd_lsbfirst_1 0=parallel data sent out msb first; 1=parallel data sent out lsb first. pcsync_conf - synchronization signals configuration for both interfaces b7 : pcts_ef_switch_1 0=pcts_ef1 pin send out the tdm frame synchronization. 1=pcts_ef1 pin send out the pc interface output error flag. b6 : pcts_synch_1 0=pcts1 set to 1 with first bit of tscc1 1=pcts1 set to 1 one pcdc cycle before the first bit of tscc . b5 : pcfs_synch_1 0=pcfs1 set to 1 with first bit of each prc . 1=pcfs1 set to 1 one pcdc cycle before the first bit of prc . b4 : pcbs_synch_1 0=pcbs1 set to 1 with the first bit of each byte. 1=pcbs1 set to 1 one pcdc cycle before the first bit of byte. b3 : pcts_ef_switch_0 0=pcts_ef0 pin send out the tdm frame synchronization. 1=pcts_ef0 pin send out the pc interface output error flag. b2 : pcts_synch_0 0=pcts0 set to 1 with first bit of tscc1 1=pcts0 set to 1 one pcdc cycle before the first bit of tscc . b1 : pcfs_synch_0 0=pcfs0 set to 1 with first bit of each prc . type: singlebyte - r/w word length: 6 byte name address (hex) bit map reset value (hex) pcsd_conf_1 0503 5-0 00 type: singlebyte - r/w word length: 7 byte name address (hex) bit map reset value (hex) pcsync_conf 0504 7-0 77
STA400A 98/117 1=pcfs0 set to 1 one pcdc cycle before the first bit of prc . b0 : pcbs_synch_0 0=pcbs0 set to 1 with the first bit of each byte. 1=pcbs0 set to 1 one pcdc cycle before the first bit of byte. pc_alarm - alarm signal for interface #0 and #1 b1 : pc_alarm_1 1=data trasmission error in the interface #1; 0=interface #1 operating properly. b0 : pc_alarm_0 1=data trasmission error in the interface #0; 0=interface #0 operating properly. note: these bits are automatically set to 0 after read. type: singlebyte - r/w word length: 2 byte name address (hex) bit map reset value (hex) pc_alarm 0506 1-0 00
99/117 STA400A 2.8 tdm (section 2) deltarefcyc_m - delta reference cycles for mcm frame sync given in samples and per mcm-frame. format: siii,fffffffff with s=sign; i=integer part; f=fractional part mfpsyncmax_s1 - sat1 mfp sync rightmost distance sets the rightmost distance of sat1 mfp sync to the point, when the frame is read. the initial value corresponds to a time of 12ms. mfpsyncmin_s1 - sat1 mfp sync leftmost distance sets the leftmost distance of sat1 mfp sync to the point, when the frame is read. the initial value corresponds to a time of 8ms. mfpsyncmax_s2 - sat2 mfp sync rightmost distance sets the rightmost distance of sat1 mfp sync to the point, when the frame is read. the initial value corresponds to a time of 12ms. mfpsyncmin_s2 - sat2 mfp sync leftmost distance sets the leftmost distance of sat1 mfp sync to the point, when the frame is read. the initial value corresponds to a time of 8ms. type: multibytes - r word length: 13 byte name address (hex) bit map reset value (hex) deltarefcyc2_m 0611 12-8 -- deltarefcyc1_m 0610 7-0 -- type: singlebyte - r/w word length: 8 byte name address (hex) bit map reset value (hex) mfpsyncmax_s1 0620 7-0 46 type: singlebyte - r/w word length: 8 byte name address (hex) bit map reset value (hex) mfpsyncmin_s1 0621 7-0 2f type: singlebyte - r/w word length: 8 byte name address (hex) bit map reset value (hex) mfpsyncmax_s2 0622 7-0 46 type: singlebyte - r/w word length: 8 byte name address (hex) bit map reset value (hex) mfpsyncmin_s2 0623 7-0 2f
STA400A 100/117 mfpsyncmax_t - terrestrial mfp sync rightmost distance mfpsyncmin_t - terrestrial mfp sync leftmost distance xmem_type - external memory device type b0 : 0= 64 mbit memory 1= 128mbit memory xmemrefcyc - external memory refresh cycle period xmemmode - external memory management mode b1-b0 : 00= normal 10= unused 01= memory dump 11= self test xmemstatus - external memory management status tdm external memory management self test error status type: singlebyte - r/w word length: 8 byte name address (hex) bit map reset value (hex) mfpsyncmax_t 0624 7-0 11 type: singlebyte - r/w word length: 8 byte name address (hex) bit map reset value (hex) mfpsyncmin_t 0625 7-0 29 type: singlebyte - r/w word length: 1 byte name address (hex) bit map reset value (hex) xmem_type 0630 0 00 type: multibytes - r/w word length: 9 byte name address (hex) bit map reset value (hex) xmemrefcyc2 0632 8 01 xmemrefcyc1 0631 7-0 75 type: singlebyte - r/w word length: 2 byte name address (hex) bit map reset value (hex) xmemmode 0634 1-0 00 type: singlebyte - r word length: 2 byte name address (hex) bit map reset value (hex) xmemstatus 0635 1-0 --
101/117 STA400A b1-b0 : 00= no error 10= unused 01= memory error, 1st test sequence 11= memory error, 2nd test sequence xmemsterradr - external memory management self-test error address tdm external memory error address. only one error address will be stored. b23-b12 : row address b11-b9 : memory bank number b8-b0 : column address udcycdelta_t - mfp cycle number up-down delta sets the number of system clock cycles the mfp cycle number is shortened or extended if tdm_rd_sync is not at the allowed position. this register influences delta_ref_cyc. cnt_prio - mfp cycles time interval setting sets the time interval in mfp cycles the priority is decremented udcycles - mfp cycle number adjustment sets the number of system clock cycles the mfp cycle number is shortened or extended if tdm_rd_sync is not at the allowed position. this directly influences the jitter of the mfp clock. type: multibytes - r word length: 24 byte name address (hex) bit map reset value (hex) xmemsterradr3 0638 23-9 -- xmemsterradr2 0637 15-8 -- xmemsterradr1 0636 7-0 -- type: multibytes - r/w word length: 11 byte name address (hex) bit map reset value (hex) udcycdelta2_t 0641 10-8 00 udcycdelta1_t 0640 7-0 00 type: singlebyte - r/w word length: 8 byte name address (hex) bit map reset value (hex) cnt_prio 0642 7-0 80 type: multibytes - r/w word length: 11 byte name address (hex) bit map reset value (hex) udcycles2 0644 10-8 00 udcycles1 0643 7-0 9c
STA400A 102/117 framelen - tdm frame length sets the nominal tdm frame length in system clock cycles. this value is used for the prediction of the mfp clock. the default value corresponds to 432ms at nominal system clock. deltacycles - mfp clock period monitor displays the deviation of the actual mfp clock period from the nominal value set in register framelen (0x0645/ 46/47). the value is given in number of system clock cycles. mfc - master frame counter mfc_lsb - master frame counter (lsb) tdm2enable - tdm management block enable this register enables/disables the tdm2 internal blocks. the single block is enabled loading '1' in the corre- sponding bit. type: multibytes - r/w word length: 24 byte name address (hex) bit map reset value (hex) framelen3 0647 23-9 9d framelen2 0646 15-8 ad framelen1 0645 7-0 00 type: multibytes - r word length: 11 byte name address (hex) bit map reset value (hex) deltacycles2 0649 10-8 -- deltacycles1 0648 7-0 -- type: multibytes - r word length: 11 byte name address (hex) bit map reset value (hex) mfc2 064b 10-8 -- mfc1 064a 7-0 -- type: singlebyte - r word length: 7 byte name address (hex) bit map reset value (hex) mfc_lsb 064c 6-0 -- type : singlebyte - r/w word length: 8 byte name address (hex) bit map reset value (hex) tdm2enable 064d 7-0 ff
103/117 STA400A b7 : trs_en enable tdm read synchronization b6 : mcg_en enable mfp clock generation b5 : pdc_en enable prc demultiplex controller b4 : trm_en enable tdm read management b3 : tam_en enable tdm external memory access management b2 : tmc_en enable tdm external memory controller b1 : twm_en enable tdm write management b0 : trb_en enable tdm bookkeeping xmemfifolevel - external memory write access buffer filling level external memory write access buffer filling level. maximum value is 12dec. pciddatard - pcid table read register using this register the internal prc demux table can be read together with the address register pcidaddr ( 0x0653) . in this register the pcid value together with the control flags for both pc interfaces is provided. pciddatawr1 (0x0651) contains the pcid number. pciddatawr2 (0x0652) contains whether the pcid interface 0 (b8) or 1 (b9) is enabled (=1) or disabled (=0) pciddatawr - pcid number write and pc interface port enable using this register the internal prc demux table can be configured together with the address register pcidaddr (0x0653). in this register the pcid value together with the control flags for both pc interfaces is provided. pciddatawr1 (0x0651) contains the pcid number. pciddatawr2 (0x0652) contains whether the pcid interface 0 (b8) or 1 (b9) is enabled (=1) or disabled (=0) pcidaddr - payload channel identifier table address using this register the internal prc demux table can be configured. the table has 28dec entries. this register holds the address where the pcid entry contained in register pciddatawr (0x0652/51) is written into the table. in order to program the pcid table this register has to be set first. starting with writing of pciddatawr, the entry type: singlebyte - r word length: 4 byte name address (hex) bit map reset value (hex) xmemfifolevel 064e 3-0 -- type: multibytes - r word length: 10 byte name address (hex) bit map reset value (hex) pciddatard2 0650 9-8 -- pciddatard1 064f 7-0 -- type: multibytes - wrt word length: 10 byte name address (hex) bit map reset value (hex) pciddatawr2 0652 9-8 00 pciddatawr1 0651 7-0 00
STA400A 104/117 is taken over into the internal pcid table. prc_ti - time interval between two prcs the number written in this register must be multiplied by 1024 to get the time interval (in number of master clock cycles ). clock cycles between two prcs: prc_ti * 1024 + 1. since there are maximum 50 prcs in a 432ms frame, with the reset value of this register the prcs in the frame occupy the following time interval: warning: this value must be greater than 8 and less than 202 to have a correct function of the pc interface. tscw_err - action setting after uncorrected tscw determines the behaviour in case of an uncorrected tscc1 of a tdm frame, i.e. possible corrupted tscw. b1-b0 : 00 = the tscw of the last received error free tdm frame are used for decoding the pcs 01 = no pcs are decoded in case of tscc1 rs uncorrected errors 10 = the received tscws are used for decoding 11 = not valid. tscw_addrrd - word address in the tscw table this register addresses the word in the tscw table the user wants to read. whenever register tscw_data (0x0657) is read, this address is automatically incremented. type: singlebyte - r/w word length: 5 byte name address (hex) bit map reset value (hex) pcidaddr 0653 4-0 00 type: singlebyte - r/w word length: 8 byte name address (hex) bit map reset value (hex) prc_ti 0654 7-0 c8 type: singlebyte - r/w word length: 2 byte name address (hex) bit map reset value (hex) tscw_err 0655 1-0 00 type: singlebyte - wrt word length: 8 byte name address (hex) bit map reset value (hex) tscw_addrrd 0656 7-0 00 116 1024 1 + 23.92 s 6 ------------------------------------- 50 248.3ms =
105/117 STA400A tscw_data - addressed tscw word contents contains the tscw word which shall be read. statuserr_t - management error and error flag if trm_error=1 the next time interval has been started although not all data of the previous time interval have been processed. b1 : trm_error tdm read management error flag b0 : trm_status 0= tdm read management disabled 1= tdm read management operational mgmtctrl_t - tdm management control vector if trm_first_proc=0/1 the satellite/terrestrial prc packet is processed first in a time interval. if trm_terr_sat_comb_en=1 both terrestrial and satellite prc packets are read. if trm_terr_sat_comb_en=0 only the prc packets indicated by trm_first_proc (0:sat, 1:terr) are processed. b3 : trm_sat_format 0= satellite data from sdram in 2's complement 1= satellite data from sdram in offset binary b2 : trm_terr_format 0= terrestrial data from sdram in 2's complement 1= terrestrial data from sdram in offset binary b1 : trm_terr_sat_comb_en 0= terr-sat combining disabled 1= terr-sat combining enabled b0 : trm_first_proc 0= satellite prc packet first 1= terrestrial prc packet first tswc_addcurr - tscw table current register address type: singlebyte - rt word length: 8 byte name address (hex) bit map reset value (hex) tscw_data 0657 7-0 -- type: singlebyte - r word length: 2 byte name address (hex) bit map reset value (hex) statuserr_t 0658 1-0 -- type: singlebyte - r/w word length: 4 byte name address (hex) bit map reset value (hex) mgmtctrl_t 0659 3-0 03 type: singlebyte - r word length: 8 byte name address (hex) bit map reset value (hex) tscw_addcurr 065b 7-0 --
STA400A 106/117 bk1-bk144 - tdm management book-keeping matrix irqmask_t - tdm interrupt mask b2 :rfu b1 :rfu b0 :rfu irqstatus_t - tdm interrupt status b2 :rfu b1 :rfu b0 :rfu 2.9 terrestrial demodulator (section 2) cfcntgood_m - counter for coarse frequency good event each time the coarse frequency calculates a new estimate that is good and is delivered to the frequency con- trol this counter is incremented. type: singlebyte - trt word length: 8 byte name address (hex) bit map reset value (hex) bk1 0661 7-0 ff bk2 0662 7-0 ff ... ... ... ... bk144 06f0 7-0 ff type: singlebyte - int word length : 3 byte name address (hex) bit map reset value (hex) irqmask_t 06f5 2-0 00 type: singlebyte - int word length: 3 byte name address (hex) bit map reset value (hex) irqstatus_t 06f6 2-0 00 type: multibytes - pr word length: 16 byte name address (hex) bit map reset value (hex) cfcntgood2_m 0711 15-8 00 cfcntgood1_m 0710 7-0 00
107/117 STA400A cfcntbad_m - counter for coarse frequency bad event each time the coarse frequency calculates a new estimate that is bad (and then not used) this counter is in- cremented. cfctrl_m - coarse frequency control b0 : use_all_amss 0=use amss samples only in case of frame sync detection. 1=use amss samples even predidted ones. cf_minkexplow_m - coarse frequency estimation confidence threshold control of threshold value for good/bad decision of cf algorithm. this value determines the absolute minimum of the confidence threshold value for the distinction between good and bad estimates independently of the his- tory stored within the sliding window buffer (see register 0x072d). cf_diffkexpmaxlow_m - coarse frequency estimation confidence threshold control of threshold value for good/bad decision of cf algorithm. this value is used to determine the relative min- imum of the confidence threshold value for the distinction between good and bad estimates dependent on the maximum frequency estimate confidence value stored in the sliding window buffer (see register 0x072d). the relative minimum is calculated by the maximum estimate confidence value within the sliding window buffer mi- nus the register value. the maximum value of both absolute and relative minimum values determines the lowest confidence threshold used by the algorithm. cf_delta_kexplow_m - coarse frequency estimation confidence threshold control of threshold value for good/bad decision of cf algorithm. this value is the decrement of the threshold type: multibytes - pr word length: 16 byte name address (hex) bit map reset value (hex) cfcntbad2_m 0716 15-8 00 cfcntbad1_m 0715 7-0 00 type: singlebyte - r/w word length: 1 byte name address (hex) bit map reset value (hex) cfctrl_m 0708 0 00 type: singlebyte - r/w word length: 8 byte name address (hex) bit map reset value (hex) cf_minkexplow_m 0720 7-0 90 type: singlebyte - r/w word length: 8 byte name address (hex) bit map reset value (hex) cf_diffkexpmaxlow_m 0721 7-0 08
STA400A 108/117 value each time the algorithm lowers the confidence threshold due to bad estimates. cf_deltacntlow_m - coarse frequency estimation confidence threshold coarse frequency estimation confidence threshold control. this value is the number of subsequent bad es- timates for lowering the confidence threshold by a decrement of register 0x0722 cf_maxkexphigh_m - coarse frequency estimation confidence threshold control of threshold value for good/bad decision of cf algorithm. this value determines the absolute maximum of the confidence threshold value for the distinction between good and bad estimates independent of the history stored within the sliding window buffer (see register 0x072d). cf_diffkexpmaxhigh_m - coarse frequency estimation confidence threshold control of threshold value for good/bad decision of cf algorithm. this value is used to determine the relative maximum of the confidence threshold value for the distinction between good and bad estimates dependent on the maximum frequency estimate confidence value stored in the sliding window buffer (see register 0x072d). the relative maximum is calculated by the maximum estimate confidence value within the sliding window buffer minus the register value. the minimum value of both absolute and relative maximum values determines the highest confidence threshold used by the algorithm. cf_deltakexphigh_m - coarse frequency estimation confidence threshold control of threshold value for good/bad decision of cf algorithm. this value is the increment of the threshold value each time the algorithm enlarges the confidence threshold due to good estimates. type: singlebyte - r/w word length: 8 byte name address (hex) bit map reset value (hex) cf_delta_kexplow_m 0722 7-0 01 type: singlebyte - r/w word length: 10 byte name address (hex) bit map reset value (hex) cf_deltacntlow2_m 0724 9-8 00 cf_deltacntlow1_m 0723 7-0 20 type: singlebyte - r/w word length: 8 byte name address (hex) bit map reset value (hex) cf_maxkexphigh_m 0726 7-0 ff type: singlebyte - r/w word length: 8 byte name address (hex) bit map reset value (hex) cf_diffkexpmaxhigh_m 0727 7-0 06 type: singlebyte - r/w word length: 8 byte name address (hex) bit map reset value (hex) cf_deltakexphigh_m 0728 7-0 01
109/117 STA400A cf_deltacnthigh_m - coarse frequency estimation confidence threshold this value is the number of subsequent good estimates for enlarging the confidence threshold by an increment of register 0x0728 cf_initdelay_m - coarse frequency estimation initial delay this value determines the minimum number of amss estimates stored in the sliding window average before the first estimate is put out. for the calculation of the first cf estimate, cf_initdelay_m+1 estimates are taken into account. within the initial phase no confidence threshold is applied and all estimates are good. nevertheless the confidence threshold is calculated and used for the cf_initdelay_m+2 nd estimate. cf_kexpthact_m - current confidence threshold value this register hold the current confidence threshold value the cf algorithm takes to distinguish between good and bad coarse frequency estimates. if the internally calculated confidence value is equal or larger than the current threshold the estimate is considered as good. cf_estact_m - coarse frequency estimation of amss before averaging with each received amss sequence a new frequency estimate is calculated together with a confidence value. then an averaging over good estimates is performed. within this register the coarse frequency estimate of the received amss before averaging is held. type: singlebyte - r/w word length: 10 byte name address (hex) bit map reset value (hex) cf_deltacnthigh2_m 072a 9-8 00 cf_deltacnthigh1_m 0729 7-0 01 type: singlebyte - r/w word length: 5 byte name address (hex) bit map reset value (hex) cf_initdelay_m 072b 4-0 17 type: singlebyte - r word length: 8 byte name address (hex) bit map reset value (hex) cf_kexpthact_m 072d 7-0 -- type: singlebyte - r/w word length: 16 byte name address (hex) bit map reset value (hex) cf_estact2_m 0731 15-8 -- cf_estact1_m 0730 7-0 --
STA400A 110/117 cf_kexpactexp_m - coarse frequency confidence exponent of amss before averaging with each received amss sequence a new frequency estimate is calculated together with a confidence value. then an averaging over good estimates is performed. within this register the confidence exponent of the coarse frequency estimate of the received amss before averaging is held. cf_est_m - coarse frequency estimation of amss after averaging with each received amss sequence a new frequency estimate is calculated together with a confidence value. then an averaging over good estimates is performed. within this register the coarse frequency estimate of the received amss after averaging is held. cf_estexp_m - coarse frequency confidence exponent of amss after averaging with each received amss sequence a new frequency estimate is calculated together with a confidence value. then an averaging over good estimates is performed. within this register the confidence exponen of the coarse frequency estimate of the received amss after averaging is held. _ avgest_m - current coarse frequency averager estimates this register shows the current cf estimate after the mcm cf averager which is applied to the mcm frequency control. with each received cf estimate an new averaged cf estimte is put out when the corresponding con- fidence value exceeds the required threshold. type: singlebyte - r word length: 8 byte name address (hex) bit map reset value (hex) cf_kexpactexp_m 0735 7-0 -- type: singlebyte - r/w word length: 16 byte name address (hex) bit map reset value (hex) cf_est2_m 0741 15-8 -- cf_est1_m 0740 7-0 -- type: singlebyte - r word length: 8 byte name address (hex) bit map reset value (hex) cf_estexp_m 0745 7-0 -- type: singlebyte - r/w word length: 16 byte name address (hex) bit map reset value (hex) cf_avgest2_m 0751 15-8 -- cf_avgest1_m 0750 7-0 --
111/117 STA400A cf_avgestexp_m - current coarse frequency averager confidence estimates this register shows the cf confidence value after the mcm cf averager block. this confidence value is applied to the mcm frequency control. cf_avgctrl - coarse frequency averager control register b7 : avg_en 0 = disabled; 1 = enabled b6 : init_th_en 0 = disabled; 1 = enabled b5-b3 : avg_len tbd b2-b0 : init_avg_delay tbd cf_avgminestconf - threshold for coarse frequency confidence type: singlebyte - r word length: 8 byte name address (hex) bit map reset value (hex) cf_avgestexp_m 0755 7-0 -- type: singlebyte - r/w word length: 8 byte name address (hex) bit map reset value (hex) cf_avgctrl 0780 7-0 b0 type: singlebyte - r/w word length: 8 byte name address (hex) bit map reset value (hex) cf_avgctrl 0780 7-0 b0
STA400A 112/117 3 i/o cell description 1) cmos output pad buffer , 2ma with slew rate control. 2) cmos output pad buffer , 4ma with slew rate control. 3) cmos schmitt trigger input pad buffer 4) cmos bidir pad buffer, 2ma with slew rate control. 5) cmos schmitt trigger bidir pad buffer, 4ma with slew rate control a d98au920 z external pin max. load z 50pf a d98au920 z external pin max. load z 100pf a d99au1072 z external pin capacitance a1pf en a zi d99au1074 a io external pin input cap max. load i/o 1.5pf 50pf en a d98au921 zi io external pin input cap max. load i/o 1.9pf 100pf
113/117 STA400A 6) cmos input pad buffer, high drive 7) cmos input pad buffer with active pull-down (50k w resistor) 8) analog pad buffer max voltage swing min: gnd-0.8 v max: vdd+0.8 v vdd = 1.8 v a d98au906 z external pin capacitance a 1.0pf a d98au923 z external pin capacitance a 1.0pf i/o 460 d02au1414 z i/o external pin input cap max. load i/o (when input) 1.9pf i/o (when output) 200pf
STA400A 114/117 9 timing diagrams 9.1 ac characterictics (guaranteed by design) figure 17. clocks and i/o timing diagram load circuit: 50 pf to ground. symbol parameter min max unit t wh clock high pulse width 6 nsec t wl clock low pulse width 6 nsec t rxc rise delay (xti/mclk clock input to mclko clock output) 7nsec t rxcn rise delay (xti/mclk clock input to mclkon clock output) 10 nsec t fxc fall delay (xti/mclk clock input to mclko clock output) 7nsec t fxcn fall delay (xti/mclk clock input to mclkon clock output) 9nsec t su input set-up time 1 nsec t hold input hold time 5 nsec t dxo output data valid delay 13 nsec t su if2td[9:0] if2sd[7:0] mai1 mdq[7:0] t hold t rxc t fxcn t fxc t rxcn xti/mclk mclko mclkon t wh t wl data(1) data(2) data(3) t dxo digital outputs
115/117 STA400A 9.2) output buffer drive characterictics (guaranteed by design) figure 18. slew rate load circuit 1) see pin description. 2) load circuit: see fig.17. 3) the current slew rate values are the mean values between currents in vdd=3.3v and gnd power lines for one buffer. 4) typical peak current in gnd: 24ma. 5) typical peak current in gnd: 50ma. 6) temperature 25 c, vdd=3.3v. symbol parameter buffer codition min typ max unit rvsr rise voltage slew rate 2ma driver 1) with load 2) 0.8 1.2 1.9 v/ns no load) 4.0 6.1 8.3 v/ns fvsr fall voltage slew rate 2ma driver with load 2) 0.8 1.2 1.9 v/ns no load 3.6 5.3 7.9 v/ns rvsr rise voltage slew rate 4ma driver 1) with load 2) 1.1 1.8 2.8 v/ns no load 4.6 6.8 9.6 v/ns fvsr fall voltage slew rate 4ma driver with load 2) 1.2 1.8 2.6 v/ns no load 3.8 5.4 9.2 v/ns csr 3) current slew rate 2ma driver 4) 35pf load 6) 8.0 ma/ns 4ma driver 5) 35pf load 6) 6.0 ma/ns 10pf 1 kohm 1 kohm vdd3 vr 0.2*vdd3 0.6*vdd3 vf tf tr rvsr=vr/tr fvsr=vf/tf
STA400A 116/117 outline and mechanical data dim. mm inch min. typ. max. min. typ. max. a 1.60 0.063 a1 0.05 0.15 0.002 0.006 a2 1.35 1.40 1.45 0.053 0.055 0.057 b 0.17 0.22 0.27 0.007 0.009 0.011 c 0.09 0.20 0.003 0.008 d 22.00 0.866 d1 20.00 0.787 d3 17.50 0.689 e 0.50 0.020 e 22.00 0.866 e1 20.00 0.787 e3 17.50 0.689 l 0.45 0.60 0.75 0.018 0.024 0.030 l1 1.00 0.0393 k 3.5? (min.), 7?(max.) tqfp144 (20x20x1.40mm) 0099183 note 1: exact shape of each corner is optional
information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners ? 2003 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states www.st.com 117/117 STA400A

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